| Message ID | 1587729844-20798-2-git-send-email-bharat.kumar.gogada@xilinx.com |
|---|---|
| State | New |
| Headers | show |
| Series | Adding support for Versal CPM as Root Port driver | expand |
On Fri, Apr 24, 2020 at 05:34:03PM +0530, Bharat Kumar Gogada wrote: > Add device tree binding documentation for Versal CPM Root Port driver. > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > --- > .../devicetree/bindings/pci/xilinx-versal-cpm.txt | 68 ++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt DT bindings need to Cc DT list to be reviewed. Bindings are now in DT schema format. See Documentation/devicetree/writing-schema.rst. Sorry to tell you this on v6, but first I'm seeing it. > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > new file mode 100644 > index 0000000..eac6144 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > @@ -0,0 +1,68 @@ > +* Xilinx Versal CPM DMA Root Port Bridge DT description > + > +Required properties: > +- #address-cells: Address representation for root ports, set to <3> > +- #size-cells: Size representation for root ports, set to <2> > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > +- compatible: Should contain "xlnx,versal-cpm-host-1.00" > +- reg: Should contain configuration space (includes bridge registers) and > + CPM system level control and status registers, and length > +- reg-names: Must include the following entries: > + "cfg": configuration space region and bridge registers > + "cpm_slcr": CPM system level control and status registers > +- interrupts: Should contain AXI PCIe interrupt > +- interrupt-map-mask, > + interrupt-map: standard PCI properties to define the mapping of the > + PCI interface to interrupt numbers. > +- bus-range: Range of bus numbers associated with this controller > +- ranges: ranges for the PCI memory regions (I/O space region is not > + supported by hardware) > + Please refer to the standard PCI bus binding document for a more > + detailed explanation > +- msi-map: Maps a Requester ID to an MSI controller and associated MSI > + sideband data > +- interrupt-names: Must include the following entries: > + "misc": interrupt asserted when legacy or error interrupt is received Don't really need a name when only 1. > + > +Interrupt controller child node > ++++++++++++++++++++++++++++++++ > +Required properties: > +- interrupt-controller: identifies the node as an interrupt controller > +- #address-cells: specifies the number of cells needed to encode an > + address. The value must be 0. > +- #interrupt-cells: specifies the number of cells needed to encode an > + interrupt source. The value must be 1. > + > + > +Refer to the following binding document for more detailed description on > +the use of 'msi-map': > + Documentation/devicetree/bindings/pci/pci-msi.txt > + > +Example: > + pci@fca10000 { Unit address is normally the first entry. > + #address-cells = <3>; > + #interrupt-cells = <1>; > + #size-cells = <2>; > + compatible = "xlnx,versal-cpm-host-1.00"; > + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, > + <0 0 0 2 &pcie_intc_0 1>, > + <0 0 0 3 &pcie_intc_0 2>, > + <0 0 0 4 &pcie_intc_0 3>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-parent = <&gic>; > + interrupt-names = "misc"; > + interrupts = <0 72 4>; > + bus-range = <0x00 0xff>; > + ranges = <0x02000000 0x00000000 0xE0000000 0x0 0xE0000000 0x00000000 0x10000000>, lowercase hex please. > + <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; > + msi-map = <0x0 &its_gic 0x0 0x10000>; > + reg = <0x6 0x00000000 0x0 0x10000000>, > + <0x0 0xFCA10000 0x0 0x1000>; > + reg-names = "cfg", "cpm_slcr"; > + pcie_intc_0: pci-interrupt-controller { interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller ; > + }; > + }; > -- > 2.7.4 >
> On Fri, Apr 24, 2020 at 05:34:03PM +0530, Bharat Kumar Gogada wrote: > > Add device tree binding documentation for Versal CPM Root Port driver. > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > > --- > > .../devicetree/bindings/pci/xilinx-versal-cpm.txt | 68 > > ++++++++++++++++++++++ > > 1 file changed, 68 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > DT bindings need to Cc DT list to be reviewed. Bindings are now in DT schema > format. See Documentation/devicetree/writing-schema.rst. > > Sorry to tell you this on v6, but first I'm seeing it. Hi Rob, Thanks for the inputs, will fix this and send with schema format. Regards, Bharat > > > > > diff --git > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > new file mode 100644 > > index 0000000..eac6144 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt > > @@ -0,0 +1,68 @@ > > +* Xilinx Versal CPM DMA Root Port Bridge DT description > > + > > +Required properties: > > +- #address-cells: Address representation for root ports, set to <3> > > +- #size-cells: Size representation for root ports, set to <2> > > +- #interrupt-cells: specifies the number of cells needed to encode an > > + interrupt source. The value must be 1. > > +- compatible: Should contain "xlnx,versal-cpm-host-1.00" > > +- reg: Should contain configuration space (includes bridge registers) and > > + CPM system level control and status registers, and length > > +- reg-names: Must include the following entries: > > + "cfg": configuration space region and bridge registers > > + "cpm_slcr": CPM system level control and status registers > > +- interrupts: Should contain AXI PCIe interrupt > > +- interrupt-map-mask, > > + interrupt-map: standard PCI properties to define the mapping of the > > + PCI interface to interrupt numbers. > > +- bus-range: Range of bus numbers associated with this controller > > +- ranges: ranges for the PCI memory regions (I/O space region is not > > + supported by hardware) > > + Please refer to the standard PCI bus binding document for a more > > + detailed explanation > > +- msi-map: Maps a Requester ID to an MSI controller and associated MSI > > + sideband data > > +- interrupt-names: Must include the following entries: > > + "misc": interrupt asserted when legacy or error interrupt is > > +received > > Don't really need a name when only 1. > > > + > > +Interrupt controller child node > > ++++++++++++++++++++++++++++++++ > > +Required properties: > > +- interrupt-controller: identifies the node as an interrupt > > +controller > > +- #address-cells: specifies the number of cells needed to encode an > > + address. The value must be 0. > > +- #interrupt-cells: specifies the number of cells needed to encode an > > + interrupt source. The value must be 1. > > + > > + > > +Refer to the following binding document for more detailed description > > +on the use of 'msi-map': > > + Documentation/devicetree/bindings/pci/pci-msi.txt > > + > > +Example: > > + pci@fca10000 { > > Unit address is normally the first entry. > > > + #address-cells = <3>; > > + #interrupt-cells = <1>; > > + #size-cells = <2>; > > + compatible = "xlnx,versal-cpm-host-1.00"; > > + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, > > + <0 0 0 2 &pcie_intc_0 1>, > > + <0 0 0 3 &pcie_intc_0 2>, > > + <0 0 0 4 &pcie_intc_0 3>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-parent = <&gic>; > > + interrupt-names = "misc"; > > + interrupts = <0 72 4>; > > + bus-range = <0x00 0xff>; > > + ranges = <0x02000000 0x00000000 0xE0000000 0x0 > 0xE0000000 > > +0x00000000 0x10000000>, > > lowercase hex please. > > > + <0x43000000 0x00000080 0x00000000 0x00000080 > 0x00000000 0x00000000 0x80000000>; > > + msi-map = <0x0 &its_gic 0x0 0x10000>; > > + reg = <0x6 0x00000000 0x0 0x10000000>, > > + <0x0 0xFCA10000 0x0 0x1000>; > > + reg-names = "cfg", "cpm_slcr"; > > + pcie_intc_0: pci-interrupt-controller { > > interrupt-controller { > > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + interrupt-controller ; > > + }; > > + }; > > -- > > 2.7.4 > >
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt new file mode 100644 index 0000000..eac6144 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt @@ -0,0 +1,68 @@ +* Xilinx Versal CPM DMA Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to <3> +- #size-cells: Size representation for root ports, set to <2> +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain "xlnx,versal-cpm-host-1.00" +- reg: Should contain configuration space (includes bridge registers) and + CPM system level control and status registers, and length +- reg-names: Must include the following entries: + "cfg": configuration space region and bridge registers + "cpm_slcr": CPM system level control and status registers +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- bus-range: Range of bus numbers associated with this controller +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation +- msi-map: Maps a Requester ID to an MSI controller and associated MSI + sideband data +- interrupt-names: Must include the following entries: + "misc": interrupt asserted when legacy or error interrupt is received + +Interrupt controller child node ++++++++++++++++++++++++++++++++ +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + + +Refer to the following binding document for more detailed description on +the use of 'msi-map': + Documentation/devicetree/bindings/pci/pci-msi.txt + +Example: + pci@fca10000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,versal-cpm-host-1.00"; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&gic>; + interrupt-names = "misc"; + interrupts = <0 72 4>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x00000000 0xE0000000 0x0 0xE0000000 0x00000000 0x10000000>, + <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x6 0x00000000 0x0 0x10000000>, + <0x0 0xFCA10000 0x0 0x1000>; + reg-names = "cfg", "cpm_slcr"; + pcie_intc_0: pci-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + };
Add device tree binding documentation for Versal CPM Root Port driver. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> --- .../devicetree/bindings/pci/xilinx-versal-cpm.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.txt