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Fri, 13 Dec 2019 13:13:48 +0000 (GMT) From: Anvesh Salveru To: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: kishon@ti.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, andrew.murray@arm.com, bhelgaas@google.com, pankaj.dubey@samsung.com, mark.rutland@arm.com, robh+dt@kernel.org, Anvesh Salveru Subject: [PATCH v6 2/2] PCI: dwc: add support to handle ZRX-DC Compliant PHYs Date: Fri, 13 Dec 2019 18:43:20 +0530 Message-Id: <1576242800-23969-3-git-send-email-anvesh.s@samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576242800-23969-1-git-send-email-anvesh.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgleLIzCtJLcpLzFFi42LZdlhTS7e/73OsQeNTDovm/9tZLc7uWshq saQpw2LX3Q52ixVfZrJbXHjaw2ZxedccNouz846zWbz5/YLdYun1i0wWi7Z+Ybdo3XuE3YHH Y828NYweO2fdZfdYsKnUY9OqTjaPvi2rGD227P/M6HH8xnYmj8+b5AI4orhsUlJzMstSi/Tt ErgyHk5bzVKwRqjiwKTLzA2Mx/m7GDk5JARMJA5sPMDcxcjFISSwm1Fi94tvLCAJIYFPjBJH dilAJL4xSjQ0TGGG6bh65hQbRNFeRokJc0QhilqYJD7NPcYOkmAT0Jb4eXQvmC0iYC1xuH0L WAOzwD9GicdzKroYOTiEBfwlzi4Bm8kioCpxZNMjsHJeAReJNZt3skDskpO4ea4TrIZTwFVi 56MFYJdKCNxmk7ix5Q/UQS4Sr/9NY4SwhSVeHd/CDmFLSbzsb4Oy8yV67y6FsmskptztgKq3 lzhwZQ4LyD3MApoS63fpQ5zJJ9H7+wkTSFhCgFeio00IwlSSaJtZDdEoIbF4/k2oAzwkPjb1 skFCYQYw2H6uZJnAKDsLYegCRsZVjJKpBcW56anFpgVGeanlesWJucWleel6yfm5mxjB6UPL awfjsnM+hxgFOBiVeHgZUj7FCrEmlhVX5h5ilOBgVhLhTdX+HCvEm5JYWZValB9fVJqTWnyI UZqDRUmcdxLr1RghgfTEktTs1NSC1CKYLBMHp1QDY6XOWY3qN6Wb7FfFHD7VrCzpZfhqjUpr 5+ymdCXbU3m2c7c3CBY+azm5eTf/c4F5zBoMc+J7f3VNXu1i6PjiuGf22jxfs5Lveyw8X8X1 hFtdelqVVCtinBggXWv/7cKkuN6Vz7ebKwjuM1XfxHHFJGVtx0GpwDero5Jqvzj3cDw76GUe HeugxFKckWioxVxUnAgA5RbjghsDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWy7bCSvG5f3+dYg7+XBCya/29ntTi7ayGr xZKmDItddzvYLVZ8mcluceFpD5vF5V1z2CzOzjvOZvHm9wt2i6XXLzJZLNr6hd2ide8Rdgce jzXz1jB67Jx1l91jwaZSj02rOtk8+rasYvTYsv8zo8fxG9uZPD5vkgvgiOKySUnNySxLLdK3 S+DKeDhtNUvBGqGKA5MuMzcwHufvYuTkkBAwkbh65hRbFyMXh5DAbkaJjpfTmSESEhJf9n5l g7CFJVb+e84OYgsJNDFJLGmIBbHZBLQlfh7dCxYXEbCVuP9oMivIIGaBLiaJM7/ugw0SFvCV uDn5NxOIzSKgKnFk0yOwBl4BF4k1m3eyQCyQk7h5rhOsnlPAVWLnowXMEMtcJBYsvcE6gZFv ASPDKkbJ1ILi3PTcYsMCo7zUcr3ixNzi0rx0veT83E2M4BDW0trBeOJE/CFGAQ5GJR7eFYmf YoVYE8uKK3MPMUpwMCuJ8KZqf44V4k1JrKxKLcqPLyrNSS0+xCjNwaIkziuffyxSSCA9sSQ1 OzW1ILUIJsvEwSnVwNi86YaOHPvnO6uePVosHbVVuzPpdfkNzws2sYwfpG6sXL/5jnj6Jt/v bh//heWJin2avnNJ8L6DPL/LHW463ts24aGAeVwru+rDznOKTdYdn9805DZJna2vzD1395i/ Ve/CW4kP1U813BO6J5W3ZoHAg8M+M5/OyrPTUz56aRtbZ7JT8b2eDfxKLMUZiYZazEXFiQAy IuEPXQIAAA== X-CMS-MailID: 20191213131350epcas5p3c90ec8981639f488b65d8e09b098fa2b X-Msg-Generator: CA CMS-TYPE: 105P X-CMS-RootMailID: 20191213131350epcas5p3c90ec8981639f488b65d8e09b098fa2b References: <1576242800-23969-1-git-send-email-anvesh.s@samsung.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Many platforms use DesignWare controller but the PHY can be different in different platforms. If the PHY is compliant is to ZRX-DC specification it helps in low power consumption during power states. If current data rate is 8.0 GT/s or higher and PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states. DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY. Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable to specify this property to the controller. Signed-off-by: Anvesh Salveru Signed-off-by: Pankaj Dubey --- Changes w.r.t v5: - None drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 820488d..36a01b7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci) PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + + if (pci->phy_zrxdc_compliant) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5accdd6..36f7579 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -60,6 +60,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0) + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) #define PCIE_ATU_REGION_OUTBOUND 0 @@ -249,6 +252,7 @@ struct dw_pcie { void __iomem *atu_base; u32 num_viewport; u8 iatu_unroll_enabled; + bool phy_zrxdc_compliant; struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops;