From patchwork Mon Nov 27 06:20:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 841484 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="JKS9c5oH"; dkim=pass (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="JKS9c5oH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ylcBs0Lr4z9sPr for ; Mon, 27 Nov 2017 17:21:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751096AbdK0GUl (ORCPT ); Mon, 27 Nov 2017 01:20:41 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:48692 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751197AbdK0GUj (ORCPT ); Mon, 27 Nov 2017 01:20:39 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 67B2769B2B; Mon, 27 Nov 2017 06:20:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511763639; bh=b/AzsVvxqKdwld6CE+MDoACLvOI7z3Fb0/dUwCxbqTY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JKS9c5oHKU8bj4mZUB05v6lsJYfFz7JWJJbNqivAgoAORDkaPXQ9w5q1q2nSSf7tS MoqF42/F/0YNbOa6ZRzIZRC/KuUmwrSVT8XF84KT3hRK/7XdGOyfFFNbLqGhnTu0rq 6Ed0lYjfmLOCv3+ooCmbHJ1RC2A+4qkZXJ/XWax8= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3C93A69B29; Mon, 27 Nov 2017 06:20:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511763639; bh=b/AzsVvxqKdwld6CE+MDoACLvOI7z3Fb0/dUwCxbqTY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JKS9c5oHKU8bj4mZUB05v6lsJYfFz7JWJJbNqivAgoAORDkaPXQ9w5q1q2nSSf7tS MoqF42/F/0YNbOa6ZRzIZRC/KuUmwrSVT8XF84KT3hRK/7XdGOyfFFNbLqGhnTu0rq 6Ed0lYjfmLOCv3+ooCmbHJ1RC2A+4qkZXJ/XWax8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3C93A69B29 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sinan Kaya , Bjorn Helgaas , linux-kernel@vger.kernel.org (open list) Subject: [PATCH V2 3/7] PCI: make pci_flr_wait() generic and rename to pci_dev_wait() Date: Mon, 27 Nov 2017 01:20:24 -0500 Message-Id: <1511763628-11856-4-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> References: <1511763628-11856-1-git-send-email-okaya@codeaurora.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rev 3.1 Sec 2.3.1 Request Handling Rules: Valid reset conditions after which a device is permitted to return CRS are: * Cold, Warm, and Hot Resets, * FLR * A reset initiated in response to a D3hot to D0 uninitialized Try to reuse FLR implementation towards other reset types. Signed-off-by: Sinan Kaya --- drivers/pci/pci.c | 47 ++++++++++++++++++++++++++++++----------------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 27ec45d..ed3c3bc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -125,6 +125,9 @@ static int __init pcie_port_pm_setup(char *str) } __setup("pcie_port_pm=", pcie_port_pm_setup); +/* time to wait after a reset for device to become responsive */ +#define PCIE_RESET_READY_POLL_MS 60000 + /** * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children * @bus: pointer to PCI bus structure to search @@ -3820,20 +3823,13 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev) } EXPORT_SYMBOL(pci_wait_for_pending_transaction); -static int pci_flr_wait(struct pci_dev *dev) +static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) { - int delay = 1, timeout = 60000; + int delay = 1; u32 id; /* - * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within - * 100ms, but may silently discard requests while the FLR is in - * progress. Wait 100ms before trying to access the device. - */ - msleep(100); - - /* - * After 100ms, the device should not silently discard config + * After reset, the device should not silently discard config * requests, but it may still indicate that it needs more time by * responding to them with CRS completions. The Root Port will * generally synthesize ~0 data to complete the read (except when @@ -3847,14 +3843,14 @@ static int pci_flr_wait(struct pci_dev *dev) pci_read_config_dword(dev, PCI_COMMAND, &id); while (id == ~0) { if (delay > timeout) { - dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n", - 100 + delay - 1); + dev_warn(&dev->dev, "not ready %dms after %s; giving up\n", + delay - 1, reset_type); return -ENOTTY; } if (delay > 1000) - dev_info(&dev->dev, "not ready %dms after FLR; waiting\n", - 100 + delay - 1); + dev_info(&dev->dev, "not ready %dms after %s; waiting\n", + delay - 1, reset_type); msleep(delay); delay *= 2; @@ -3862,7 +3858,8 @@ static int pci_flr_wait(struct pci_dev *dev) } if (delay > 1000) - dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1); + dev_info(&dev->dev, "ready %dms after %s\n", delay - 1, + reset_type); return 0; } @@ -3899,7 +3896,15 @@ int pcie_flr(struct pci_dev *dev) dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); - return pci_flr_wait(dev); + + /* + * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within + * 100ms, but may silently discard requests while the FLR is in + * progress. Wait 100ms before trying to access the device. + */ + msleep(100); + + return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); } EXPORT_SYMBOL_GPL(pcie_flr); @@ -3932,7 +3937,15 @@ static int pci_af_flr(struct pci_dev *dev, int probe) dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); - return pci_flr_wait(dev); + + /* + * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within + * 100ms, but may silently discard requests while the FLR is in + * progress. Wait 100ms before trying to access the device. + */ + msleep(100); + + return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); } /**