From patchwork Tue Jan 3 06:34:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Jain X-Patchwork-Id: 710390 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tt42j3y59z9syB for ; Tue, 3 Jan 2017 17:35:57 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b="os7Medd9"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934583AbdACGfs (ORCPT ); Tue, 3 Jan 2017 01:35:48 -0500 Received: from mail-pg0-f49.google.com ([74.125.83.49]:36677 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934542AbdACGen (ORCPT ); Tue, 3 Jan 2017 01:34:43 -0500 Received: by mail-pg0-f49.google.com with SMTP id f188so211334146pgc.3 for ; Mon, 02 Jan 2017 22:34:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EFMxBS002LkuIs5MV5r8x2uimbWHJh64LLW+469xlEo=; b=os7Medd9bBWTTEzgVXkSnwny9v4xzwbDHcKUAQkCbFIY+Z/fVO9TKnTvQIjib7j0s/ 6r/sbXWN2ra/cb9hBCZDxgwDbTCQrQHgah9Fi8MSipHoQogJQ+AmFato34kdWWjncuAB 8DEAJASL0ac1vRA3czY6w3anIkE2H1QTihqBnQP7oh2CdA8cl6B1emgJV3PYKdLX9SrN QrsnmxYFRBajA2c4f5NdEZJzLqd2U1zHTkbH6B6odp7rtbezTB0KPTqAPcGDDl/ASrKp dVgjKXCcEpa9Tcctt+bGuvAWYgRj7sfg451hY2PldIosfq4Sy9XeMUYR4MnDzPuQXKny J9Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EFMxBS002LkuIs5MV5r8x2uimbWHJh64LLW+469xlEo=; b=k2ENdqls9Bs2yDy9d7cH2QMD9ltCBA26OhAoa/EgBPAS2/jLRlLlsoubmGCzPFOWnI QOACBkCwZQZi6Z5elotyGyYtdpGpnhZXB366O2j6ggxEEYf1Y/DpNit8F2LXcXOKeFzW uB/1EamqEURZ47UddSrb5Sp8IwiUSvtU+basWe6+yF/jQqswRoncI8xGGFQWp/cDlBVd 9fuNnW3ONGhCci346J/F13gMZImoKziESXZmcGBqqfgrZWeZnbEBM990u8GSIPed71Mg +gahmJDjdqsmUwW2GoNgkWlN5ezwSRkR1lXv5xdKnQxTIvk+TwX4Qg+B6CvliCMS4gYA udeA== X-Gm-Message-State: AIkVDXKvD4uex+dnGmwHfCunq5jTG648tLcVYf6SmvxsKs9pq/pkhT5Y11Csf39WCQBVp5Aq X-Received: by 10.84.132.129 with SMTP id e1mr132879962ple.167.1483425281335; Mon, 02 Jan 2017 22:34:41 -0800 (PST) Received: from rajat.mtv.corp.google.com ([172.22.64.13]) by smtp.gmail.com with ESMTPSA id g28sm72936251pgn.13.2017.01.02.22.34.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Jan 2017 22:34:40 -0800 (PST) From: Rajat Jain To: Bjorn Helgaas , Keith Busch , Andreas Ziegler , Jonathan Yong , Shawn Lin , David Daney , Julia Lawall , Ram Amrani , Doug Ledford , Wang Sheng-Hui , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rajat Jain , Rajat Jain , Brian Norris Subject: [PATCH 6/6] PCI/ASPM: Add comment about L1 substate latency Date: Mon, 2 Jan 2017 22:34:15 -0800 Message-Id: <1483425255-101923-7-git-send-email-rajatja@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1483425255-101923-1-git-send-email-rajatja@google.com> References: <1483425255-101923-1-git-send-email-rajatja@google.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since the exit latencies for L1 substates are not advertised by a device, it is not clear in spec how to do a L1 substate exit latency check. We assume that the L1 exit latencies advertised by a device include L1 substate latencies (and hence do not do any check). If that is not true, we should do some sort of check here. (I'm not clear about what that check should like currenlty. I'd be glad to take up any suggestions). Signed-off-by: Rajat Jain --- drivers/pci/pcie/aspm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 6735f38..cb5602c 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -403,6 +403,14 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint) * Check L1 latency. * Every switch on the path to root complex need 1 * more microsecond for L1. Spec doesn't mention L0s. + * + * The exit latencies for L1 substates are not advertised + * by a device. Since the spec also doesn't mention a way + * to determine max latencies introduced by enabling L1 + * substates on the components, it is not clear how to do + * a L1 substate exit latency check. We assume that the + * L1 exit latencies advertised by a device include L1 + * substate latencies (and hence do not do any check) */ latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); if ((link->aspm_capable & ASPM_STATE_L1) &&