diff mbox

[v2] pciutils: Add decode for Atomic Ops in lspci

Message ID 1482882756-12151-1-git-send-email-satananda.burla@caviumnetworks.com
State Not Applicable
Headers show

Commit Message

Satanand Burla Dec. 27, 2016, 11:52 p.m. UTC 
This adds support for decoding Atomic ops added in ECN
https://pcisig.com/sites/default/files/specification_documents/ECN_Atomic_Ops_080417.pdf

Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com>
---
 lib/header.h |  6 ++++++
 ls-caps.c    | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

Comments

Martin Mareš Dec. 31, 2016, 3:28 p.m. UTC | #1 
Hi!

> This adds support for decoding Atomic ops added in ECN
> https://pcisig.com/sites/default/files/specification_documents/ECN_Atomic_Ops_080417.pdf

This is much better, however, it still prints extra spaces sometimes.
Could you please fix it?

Also, I woule like to have a test case for the new code -- a configuration
space dump similar to those in tests/*. Do you have one?

				Martin
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Satanand Burla Jan. 3, 2017, 12:26 a.m. UTC | #2 
The 12/31/2016 16:28, Martin Mares wrote:
> Hi!
> 
> > This adds support for decoding Atomic ops added in ECN
> > https://pcisig.com/sites/default/files/specification_documents/ECN_Atomic_Ops_080417.pdf
> 
> This is much better, however, it still prints extra spaces sometimes.
> Could you please fix it?
> 
Can you let me know in which situation would extra spaces be printed?
Do you want me to get rid of spaces between the fields ?
The outputs look like this
Root complex:
DevCap2: Completion Timeout: Range BCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd+
AtomicOpsCap: Routing- 32bit+ 64bit+ 128bitCAS+
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
AtomicOpsCtl: ReqEn- EgressBlck-
LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-

endpoint with memory bar:
DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
AtomicOpsCtl: ReqEn-
LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-

upstream/downstream port:
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
AtomicOpsCap: Routing-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
AtomicOpsCtl: EgressBlck-
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-

> Also, I woule like to have a test case for the new code -- a configuration
> space dump similar to those in tests/*. Do you have one?
Sure.I can provide this as an updated patch.
> 
> 				Martin
Martin Mareš Feb. 9, 2017, 10:39 a.m. UTC | #3 
Hi!

> Can you let me know in which situation would extra spaces be printed?

Sorry, I misread the patch. It is correct.

So the only thing which remains to be done is a test case.

				Have a nice fortnight
Satanand Burla Feb. 10, 2017, 2:34 a.m. UTC | #4 
Hi

> Sorry, I misread the patch. It is correct.
> 
> So the only thing which remains to be done is a test case.
I have sent out the test case as another patch.
diff mbox

Patch

diff --git a/lib/header.h b/lib/header.h
index a556638..6d81cb7 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -859,7 +859,13 @@ 
 #define  PCI_EXP_DEV2_TIMEOUT_RANGE(x)	((x) & 0xf) /* Completion Timeout Ranges Supported */
 #define  PCI_EXP_DEV2_TIMEOUT_VALUE(x)	((x) & 0xf) /* Completion Timeout Value */
 #define  PCI_EXP_DEV2_TIMEOUT_DIS	0x0010	/* Completion Timeout Disable Supported */
+#define  PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN	0x0040	/* AtomicOp RequesterEnable */
+#define  PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK	0x0080	/* AtomicOp Egress Blocking */
 #define  PCI_EXP_DEV2_ARI		0x0020	/* ARI Forwarding */
+#define  PCI_EXP_DEVCAP2_ATOMICOP_ROUTING	0x0040	/* AtomicOp Routing Supported */
+#define  PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP	0x0080	/* 32bit AtomicOp Completer Supported */
+#define  PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP	0x0100	/* 64bit AtomicOp Completer Supported */
+#define  PCI_EXP_DEVCAP2_128BIT_CAS_COMP	0x0200	/* 128bit CAS Completer Supported */
 #define  PCI_EXP_DEV2_LTR		0x0400	/* LTR enabled */
 #define  PCI_EXP_DEV2_OBFF(x)		(((x) >> 13) & 3) /* OBFF enabled */
 #define PCI_EXP_DEVSTA2			0x2a	/* Device Status */
diff --git a/ls-caps.c b/ls-caps.c
index 7ff6c67..07e818f 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -961,11 +961,31 @@  static const char *cap_express_devctl2_obff(int obff)
     }
 }
 
+static int
+device_has_memory_space_bar(struct device *d)
+{
+  struct pci_dev *p = d->dev;
+  int i, found = 0;
+
+  for (i=0; i<6; i++)
+    if (p->base_addr[i] && p->size[i])
+      {
+        if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
+          {
+            found = 1;
+            break;
+          }
+      }
+  return found;
+}
+
 static void cap_express_dev2(struct device *d, int where, int type)
 {
   u32 l;
   u16 w;
+  int has_mem_bar = 0;
 
+  has_mem_bar = device_has_memory_space_bar(d);
   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
 	cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
@@ -976,6 +996,20 @@  static void cap_express_dev2(struct device *d, int where, int type)
     printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
   else
     printf("\n");
+  if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+      type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
+    {
+       printf("\t\tAtomicOpsCap:");
+       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+           type == PCI_EXP_TYPE_DOWNSTREAM)
+         printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
+       if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
+         printf(" 32bit%c 64bit%c 128bitCAS%c",
+		FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
+		FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
+		FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
+       printf("\n");
+    }
 
   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
@@ -987,6 +1021,19 @@  static void cap_express_dev2(struct device *d, int where, int type)
     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
   else
     printf("\n");
+  if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+      type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
+      type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
+    {
+      printf("\t\tAtomicOpsCtl:");
+      if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
+          type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
+        printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
+      if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
+          type == PCI_EXP_TYPE_DOWNSTREAM)
+        printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
+      printf("\n");
+    }
 }
 
 static const char *cap_express_link2_speed(int type)