From patchwork Mon Oct 24 22:17:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 686217 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t2rN86kKYz9vDW for ; Tue, 25 Oct 2016 09:21:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.b=TxzkLpMj; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S938757AbcJXWRe (ORCPT ); Mon, 24 Oct 2016 18:17:34 -0400 Received: from mail-pf0-f177.google.com ([209.85.192.177]:34925 "EHLO mail-pf0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757816AbcJXWRc (ORCPT ); Mon, 24 Oct 2016 18:17:32 -0400 Received: by mail-pf0-f177.google.com with SMTP id s8so105908947pfj.2 for ; Mon, 24 Oct 2016 15:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=elIYzpNXEQjF7pyLsPPsA3lxFYjF9nli6Ao8Dzk6oHs=; b=TxzkLpMjBR7mF6CrQtatmf74aVKFwwcQFdPaqCd1LXT14ZQ0CtRSKrDUiap0VjpcxW Wuv2AaJ9MM3l2BRvCbQeVWcNak+5LunSGmrUur/RgztjMxDFS2SIXuGhelccNuHCcdwc dDUqDW/rN4vYVW9Ffwvu3A6CYOfP90v2OaB6I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=elIYzpNXEQjF7pyLsPPsA3lxFYjF9nli6Ao8Dzk6oHs=; b=WsaVUaYyBYXBvSp0zv3xHcZBSIwHSWuZg7EU9CWm4KqjMp4Of85t1FfrkZYpc0QkTO emFjOpVEalD8+IWaXCmSyR+Uw5r6gr7pDhhUyIqGu+skUSkStg+rla22AXkcrXi5DIqL u5HYgPwnuP0/QKGIUOqkVr/FS5UK6CGpVrqDXAB+tge+feKkT8RpIel0y3Gfsr4BKDIN 8ykCKq2v0TeHgrtlEJlckciMWilrM9eB/lKRzyWxudPgJDoh2kQZOGzU7XvL+il00OUo w296zk+BI2HxFQXmZgo0QDFSxoeIyRgtN3tcx1kdwH2nMCt8o8eNX9wgKUeAtckrIP+F 6d3Q== X-Gm-Message-State: ABUngve+nf1fvWFxXVyIJgjcxiqpqmUH+QLh332qnhhOFxojf5q1/6JJYlJfe4lZOtPw9m8w X-Received: by 10.99.47.7 with SMTP id v7mr27316194pgv.15.1477347451569; Mon, 24 Oct 2016 15:17:31 -0700 (PDT) Received: from lbrmn-lnxub44-1.ric.broadcom.com ([216.31.219.19]) by smtp.gmail.com with ESMTPSA id x1sm27745131pax.7.2016.10.24.15.17.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 24 Oct 2016 15:17:31 -0700 (PDT) From: Ray Jui To: Bjorn Helgaas , Bjorn Helgaas Cc: linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, Alex Barba , Oza Oza , Ray Jui , Ray Jui Subject: [PATCH 01/12] PCI: iproc: Improve core register population Date: Mon, 24 Oct 2016 15:17:01 -0700 Message-Id: <1477347432-17656-2-git-send-email-ray.jui@broadcom.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1477347432-17656-1-git-send-email-ray.jui@broadcom.com> References: <1477347432-17656-1-git-send-email-ray.jui@broadcom.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As the number of iProc PCIe core registers starts to grow and differ between different revisions of the iProc PCIe controllers, the current way of populating each individual unsupported register with value 'IPROC_PCIE_REG_INVALID' with a table entry has become a bit messy and is difficult to scale up in the future This patch improves the current driver by populating the invalid entries with code instead of through individual table entries. This helps to avoid a significant number of invalid table entries when support for the next revision of the iProc controller is added Signed-off-by: Ray Jui Reviewed-by: Scott Branden --- drivers/pci/host/pcie-iproc.c | 83 +++++++++++++++++++++++++++++++------------ drivers/pci/host/pcie-iproc.h | 4 ++- 2 files changed, 64 insertions(+), 23 deletions(-) diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c index 0b999a9..a9b9cd8 100644 --- a/drivers/pci/host/pcie-iproc.c +++ b/drivers/pci/host/pcie-iproc.c @@ -69,18 +69,35 @@ #define IPROC_PCIE_REG_INVALID 0xffff +/* + * iProc PCIe host registers + */ enum iproc_pcie_reg { + /* clock/reset signal control */ IPROC_PCIE_CLK_CTRL = 0, + + /* allow access to root complex configuration space */ IPROC_PCIE_CFG_IND_ADDR, IPROC_PCIE_CFG_IND_DATA, + + /* allow access to device configuration space */ IPROC_PCIE_CFG_ADDR, IPROC_PCIE_CFG_DATA, + + /* enable INTx */ IPROC_PCIE_INTX_EN, + + /* outbound address mapping */ IPROC_PCIE_OARR_LO, IPROC_PCIE_OARR_HI, IPROC_PCIE_OMAP_LO, IPROC_PCIE_OMAP_HI, + + /* link status */ IPROC_PCIE_LINK_STATUS, + + /* total number of core registers */ + IPROC_PCIE_MAX_NUM_REG, }; /* iProc PCIe PAXB registers */ @@ -105,12 +122,6 @@ static const u16 iproc_pcie_reg_paxc[] = { [IPROC_PCIE_CFG_IND_DATA] = 0x1f4, [IPROC_PCIE_CFG_ADDR] = 0x1f8, [IPROC_PCIE_CFG_DATA] = 0x1fc, - [IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID, - [IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID, - [IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID, - [IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID, - [IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID, - [IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID, }; static inline struct iproc_pcie *iproc_data(struct pci_bus *bus) @@ -204,7 +215,7 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus, * PAXC is connected to an internally emulated EP within the SoC. It * allows only one device. */ - if (pcie->type == IPROC_PCIE_PAXC) + if (pcie->ep_is_internal) if (slot > 0) return NULL; @@ -232,7 +243,7 @@ static void iproc_pcie_reset(struct iproc_pcie *pcie) { u32 val; - if (pcie->type == IPROC_PCIE_PAXC) { + if (pcie->ep_is_internal) { val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL); val &= ~PAXC_RESET_MASK; iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val); @@ -270,7 +281,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus) * PAXC connects to emulated endpoint devices directly and does not * have a Serdes. Therefore skip the link detection logic here. */ - if (pcie->type == IPROC_PCIE_PAXC) + if (pcie->ep_is_internal) return 0; val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS); @@ -454,6 +465,40 @@ static void iproc_pcie_msi_disable(struct iproc_pcie *pcie) iproc_msi_exit(pcie); } +static int iproc_pcie_rev_init(struct iproc_pcie *pcie) +{ + struct device *dev = pcie->dev; + unsigned int reg_idx; + const u16 *regs; + + switch (pcie->type) { + case IPROC_PCIE_PAXB: + regs = iproc_pcie_reg_paxb; + break; + case IPROC_PCIE_PAXC: + regs = iproc_pcie_reg_paxc; + pcie->ep_is_internal = true; + break; + default: + dev_err(dev, "incompatible iProc PCIe interface\n"); + return -EINVAL; + } + + pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, + sizeof(*pcie->reg_offsets), + GFP_KERNEL); + if (!pcie->reg_offsets) + return -ENOMEM; + + /* go through the register table and populate all valid registers */ + pcie->reg_offsets[0] = regs[0]; + for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++) + pcie->reg_offsets[reg_idx] = regs[reg_idx] ? + regs[reg_idx] : IPROC_PCIE_REG_INVALID; + + return 0; +} + int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) { struct device *dev; @@ -462,6 +507,13 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) struct pci_bus *bus; dev = pcie->dev; + + ret = iproc_pcie_rev_init(pcie); + if (ret) { + dev_err(dev, "unable to initialize controller parameters\n"); + return ret; + } + ret = devm_request_pci_bus_resources(dev, res); if (ret) return ret; @@ -478,19 +530,6 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) goto err_exit_phy; } - switch (pcie->type) { - case IPROC_PCIE_PAXB: - pcie->reg_offsets = iproc_pcie_reg_paxb; - break; - case IPROC_PCIE_PAXC: - pcie->reg_offsets = iproc_pcie_reg_paxc; - break; - default: - dev_err(dev, "incompatible iProc PCIe interface\n"); - ret = -EINVAL; - goto err_power_off_phy; - } - iproc_pcie_reset(pcie); if (pcie->need_ob_cfg) { diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/host/pcie-iproc.h index e84d93c..83643d5 100644 --- a/drivers/pci/host/pcie-iproc.h +++ b/drivers/pci/host/pcie-iproc.h @@ -55,6 +55,7 @@ struct iproc_msi; * @root_bus: pointer to root bus * @phy: optional PHY device that controls the Serdes * @map_irq: function callback to map interrupts + * @ep_is_internal: indicates an internal emulated endpoint device is connected * @need_ob_cfg: indicates SW needs to configure the outbound mapping window * @ob: outbound mapping parameters * @msi: MSI data @@ -62,7 +63,7 @@ struct iproc_msi; struct iproc_pcie { struct device *dev; enum iproc_pcie_type type; - const u16 *reg_offsets; + u16 *reg_offsets; void __iomem *base; phys_addr_t base_addr; #ifdef CONFIG_ARM @@ -71,6 +72,7 @@ struct iproc_pcie { struct pci_bus *root_bus; struct phy *phy; int (*map_irq)(const struct pci_dev *, u8, u8); + bool ep_is_internal; bool need_ob_cfg; struct iproc_pcie_ob ob; struct iproc_msi *msi;