From patchwork Thu Sep 22 22:38:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Jain X-Patchwork-Id: 673743 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sgBHW03Htz9t1F for ; Fri, 23 Sep 2016 08:39:03 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=LDwK9ERp; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758171AbcIVWi4 (ORCPT ); Thu, 22 Sep 2016 18:38:56 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:35821 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758132AbcIVWiz (ORCPT ); Thu, 22 Sep 2016 18:38:55 -0400 Received: by mail-pa0-f47.google.com with SMTP id oz2so33366673pac.2 for ; Thu, 22 Sep 2016 15:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z6MtYX2Fsoqp9Zuw+KUnFZrqkijpFP3X/fkJd1bEvF0=; b=LDwK9ERpZP1ZOCiJVXSvSfquUYJuV2Uxf1NWuE0pi+OgEoV/cOlXyWKt/aDXlW9wBb 43Xrc3oRpuKWROGXb2zIh2LPnhcwLQb311QSZ+2XhB6G2DbJNbz+aDgeTG+Fy3d7tq/v 0/OH45VhJCLaG3dHMQLeFEIE43fDFwIJO2vZTqsnkS0JVYIYh2Zu9OM7i+WeT2kMmQO9 01tZPb6YHmEeCdfbiAEvE178yThwQIMbLnilaZ96MgzKuMRBPHEQFtuyYam2RUErOWor gJi7l03grselj6Rfg3OrXiYs7QWM25O0BKjOeDk7jWKzxr+arAv85hNFkZk3TdC9l9L1 1s5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z6MtYX2Fsoqp9Zuw+KUnFZrqkijpFP3X/fkJd1bEvF0=; b=Tns9M05MCZ3ZeObl70qmFVjJt5C250xaA6LhufaO/BfViYqEPmk8JK6DgoNDj+48bX rASOCGrAQMHlfGv5RKzoSLTpmUjxFnP2cwSNB+yKkOXWhO6V01yAYRInMqgaBWUF1HtL PdL126ZtoQmMEbxA7DOIEvy/jx+a1h2Z/nwnJyBUePom71YKx1qy5/0A9RU3idn52KXp kBEpVW25oHJRVkq15Fm4q+GCisU2PZ4gzuDXGbvwvcKxZjII/MXXKbTG14NJOLXinc4F gH6A0PskqJzvgrGM3ynupKiQPP1nJRI7wNOIPP3mTBkhBt8NBCYkx05T1itOKbaNekr3 NZ2g== X-Gm-Message-State: AE9vXwP78BECvXFFID4zj+blN+RvQj45qOpowlAwEtTJm2Oygjn9+xitEhjoLFygJ22hnPj1 X-Received: by 10.66.145.73 with SMTP id ss9mr7402027pab.82.1474583934589; Thu, 22 Sep 2016 15:38:54 -0700 (PDT) Received: from rajat.mtv.corp.google.com ([172.22.64.13]) by smtp.gmail.com with ESMTPSA id ak3sm6367905pad.19.2016.09.22.15.38.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Sep 2016 15:38:54 -0700 (PDT) From: Rajat Jain To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Lin , Jeffy Chen , Wenrui Li , Brian Norris Cc: Rajat Jain , rajatxjain@gmail.com Subject: [PATCH v2] PCI: rockchip: Increase the Max Credit update interval. Date: Thu, 22 Sep 2016 15:38:12 -0700 Message-Id: <1474583892-8936-1-git-send-email-rajatja@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1474578027-64292-1-git-send-email-rajatja@google.com> References: <1474578027-64292-1-git-send-email-rajatja@google.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This increases the likelihood of link state to automatically go to L1 and save some power. The default credit update interval of 7.5 us results in the rootport sending UpdateFC packets too often, thus reulting in the link never going to L1, and always staying in L0/L0s. The value 24 us was chosen after some experiments and peeking over the PCIe bus to see that we do enter L1 substate when there is not enough traffic on the PCIe bus. Signed-off-by: Rajat Jain Acked-by: Shawn Lin --- v2: Update the register on Phy link bandwidth changes, since the value gets lost on such events. drivers/pci/host/pcie-rockchip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index c3593e6..99e700f 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -95,6 +95,11 @@ #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 +#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020) +#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \ + (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT) #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c) #define PCIE_CORE_INT_PRFPE BIT(0) #define PCIE_CORE_INT_CRFPE BIT(1) @@ -224,6 +229,17 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); } +static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) +{ + u32 val; + + /* Update Tx credit maximum update interval */ + val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); + val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; + val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ + rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1); +} + static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, struct pci_bus *bus, int dev) { @@ -597,6 +613,7 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS); } else if (reg & PCIE_CLIENT_INT_PHY) { dev_dbg(dev, "phy link changes\n"); + rockchip_pcie_update_txcredit_mui(rockchip); rockchip_pcie_clr_bw_int(rockchip); }