From patchwork Tue Sep 13 09:00:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongji Xie X-Patchwork-Id: 669245 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sYJYY2DHzz9sdn for ; Tue, 13 Sep 2016 19:00:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757371AbcIMJAs (ORCPT ); Tue, 13 Sep 2016 05:00:48 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:46368 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756467AbcIMJAr (ORCPT ); Tue, 13 Sep 2016 05:00:47 -0400 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8D8wdUV101156 for ; Tue, 13 Sep 2016 05:00:47 -0400 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 25dxu44105-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 13 Sep 2016 05:00:46 -0400 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 13 Sep 2016 03:00:42 -0600 X-IBM-Helo: d03dlp02.boulder.ibm.com X-IBM-MailFrom: xyjxie@linux.vnet.ibm.com Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id 6FB3B3E4003E; Tue, 13 Sep 2016 03:00:41 -0600 (MDT) Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u8D90fPG16712022; Tue, 13 Sep 2016 09:00:41 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF802AC043; Tue, 13 Sep 2016 05:00:40 -0400 (EDT) Received: from localhost (unknown [9.123.228.244]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id 993C2AC041; Tue, 13 Sep 2016 05:00:40 -0400 (EDT) From: Yongji Xie To: bhelgaas@google.com Cc: linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, alex.williamson@redhat.com, paulus@samba.org, aik@ozlabs.ru, gwshan@linux.vnet.ibm.com, benh@kernel.crashing.org, mpe@ellerman.id.au, zhong@linux.vnet.ibm.com Subject: [PATCH v5 4/4] PCI: Add a macro to set default alignment for all PCI devices Date: Tue, 13 Sep 2016 17:00:34 +0800 X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473757234-5284-1-git-send-email-xyjxie@linux.vnet.ibm.com> References: <1473757234-5284-1-git-send-email-xyjxie@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16091309-0012-0000-0000-0000109D47A9 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00005753; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000185; SDB=6.00757163; UDB=6.00358995; IPR=6.00530523; BA=6.00004711; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00012657; XFM=3.00000011; UTC=2016-09-13 09:00:44 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16091309-0013-0000-0000-00004565D38E Message-Id: <1473757234-5284-5-git-send-email-xyjxie@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-09-13_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609020000 definitions=main-1609130133 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When vfio passthroughs a PCI device of which MMIO BARs are smaller than PAGE_SIZE, guest will not handle the mmio accesses to the BARs which leads to mmio emulations in host. This is because vfio will not allow to passthrough one BAR's mmio page which may be shared with other BARs. Otherwise, there will be a backdoor that guest can use to access BARs of other guest. This patch adds a macro to set default alignment for all PCI devices. Then we could solve this issue on some platforms which would easily hit this issue because of their 64K page such as PowerNV platform by defining this macro as PAGE_SIZE. Signed-off-by: Yongji Xie --- arch/powerpc/include/asm/pci.h | 4 ++++ drivers/pci/pci.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h index e9bd6cf..5e31bc2 100644 --- a/arch/powerpc/include/asm/pci.h +++ b/arch/powerpc/include/asm/pci.h @@ -28,6 +28,10 @@ #define PCIBIOS_MIN_IO 0x1000 #define PCIBIOS_MIN_MEM 0x10000000 +#ifdef CONFIG_PPC_POWERNV +#define PCIBIOS_DEFAULT_ALIGNMENT PAGE_SIZE +#endif + struct pci_dev; /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 37f8062..9c61cbe 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4959,6 +4959,10 @@ static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, resource_size_t align = 0; char *p; +#ifdef PCIBIOS_DEFAULT_ALIGNMENT + align = PCIBIOS_DEFAULT_ALIGNMENT; + *resize = false; +#endif spin_lock(&resource_alignment_lock); p = resource_alignment_param; if (pci_has_flag(PCI_PROBE_ONLY)) {