From patchwork Fri Sep 9 00:05:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Jain X-Patchwork-Id: 667855 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sVctk01nlz9s2G for ; Fri, 9 Sep 2016 10:06:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=b71UdZCk; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750754AbcIIAGU (ORCPT ); Thu, 8 Sep 2016 20:06:20 -0400 Received: from mail-pf0-f172.google.com ([209.85.192.172]:35080 "EHLO mail-pf0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbcIIAGT (ORCPT ); Thu, 8 Sep 2016 20:06:19 -0400 Received: by mail-pf0-f172.google.com with SMTP id w87so23048048pfk.2 for ; Thu, 08 Sep 2016 17:06:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DN2y13Fsa1c0vE3tPUWGxlEi4bxfFxsS4MLWR3xiEd4=; b=b71UdZCkBaMS9jNNuNEKi8dL4EJOQ2/Na3nmErACMFYDusHGxe03dt3titKMf4SnFF ICEaZRjWmdAVPuXSGJ4LfLj5pInuHOyn7zVKEmlnZC59ykUuufHs+j3/KNw+nWLhEJYe 7nOVlyLUN8sCCSS0aeUjrZ6D7xgnyt7GRwr0z0SIeeHOILrL/tRCm37DFmD+sRGxajwP YzRO8ihXeR69a8ED/5DEMNeHptEC5ryrmUrMFYOVqf0yO/tEwfTRg2+3Yk0X4/Y+Sp4g /SZROZrGcyUe3CE3eW78465o5WHOV8pQnY6hM4kGiE+KET2Kbf0xk5i9CrQOVVnfR5CM 25sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DN2y13Fsa1c0vE3tPUWGxlEi4bxfFxsS4MLWR3xiEd4=; b=gUjnOWr20CvW6T8AxLeEJikx5aOSV2E8SK6Cid0UXOibki/znTQlRqIk/ErQCSFULd Ebjj/uIC0f8HHod85FsVBh7tS0Av1YZYOKI/syrDsaj9dQST94ytN1YftahHr92g3KL8 XEN+NIrH8Wnh0yIBjSPVM/XtTT1udQl9NHxNgObRaASUXm+sErxFyMuvd8Y+lUJ8+JPU w+ODWl1WPoLNG7kfRlQ3jxKrg6vVnCerRZTn50suZH07SO1A7AW8HzpwmKuxNyy6EiHC qotLaaj6+zBcfeCwY9d6EPdataPFT0D3cD1KTkcB5h1HxAaUfiWVVtXuYXFGl8gVInKv DBFQ== X-Gm-Message-State: AE9vXwPt9cXTqbcXRHo9ayRoayp1Q1MHX4lIaEOXXVzcJa6PgnGqOK6m5gpSrgS6HYS6ZMaJ X-Received: by 10.98.99.67 with SMTP id x64mr1318545pfb.26.1473379578858; Thu, 08 Sep 2016 17:06:18 -0700 (PDT) Received: from rajat.mtv.corp.google.com ([172.22.64.13]) by smtp.gmail.com with ESMTPSA id bm8sm391937pac.16.2016.09.08.17.06.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Sep 2016 17:06:18 -0700 (PDT) From: Rajat Jain To: Martin Mares , bhelgaas@google.com, linux-pci@vger.kernel.org, David Box Cc: Rajat Jain , rajatxjain@gmail.com, briannorris@google.com Subject: [PATCH v2] lspci: Parse all the L1 PM substate capability regs Date: Thu, 8 Sep 2016 17:05:30 -0700 Message-Id: <1473379530-70905-1-git-send-email-rajatja@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1472747248-60993-1-git-send-email-rajatja@google.com> References: <1472747248-60993-1-git-send-email-rajatja@google.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Parse the control registers to display all the L1 PM substate configuration information. Signed-off-by: Rajat Jain --- V2: Fix the LTR1.2 threshold scaling lib/header.h | 14 +++++++++ ls-ecaps.c | 94 ++++++++++++++++++++++++++++++++++++++++++------------------ 2 files changed, 80 insertions(+), 28 deletions(-) diff --git a/lib/header.h b/lib/header.h index 1c5968b..0341ec6 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1117,6 +1117,20 @@ #define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */ #define PCI_DPC_SOURCE 10 /* DPC Source ID */ +/* L1 PM Substates Extended Capability */ +#define PCI_L1PM_SUBSTAT_CAP 0x4 /* L1 PM Substate Capability */ +#define PCI_L1PM_SUBSTAT_CAP_PM_L12 0x1 /* PCI-PM L1.2 Supported */ +#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */ +#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */ +#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */ +#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 Pm Substates supported */ +#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */ +#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */ +#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */ +#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 0x4 /* ASPM L1.2 Enable */ +#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */ +#define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/ls-ecaps.c b/ls-ecaps.c index 5e18e06..40f8cb9 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -527,55 +527,93 @@ cap_evendor(struct device *d, int where) BITS(hdr, 20, 12)); } +static inline int l1pm_calc_pwron(int scale, int value) +{ + switch (scale) + { + case 0: + return 2 * value; + case 1: + return 10 * value; + case 2: + return 100 * value; + } + return -1; +} + static void cap_l1pm(struct device *d, int where) { - u32 l1_cap; - int power_on_scale; + u32 l1_cap, val, scale; + int time; printf("L1 PM Substates\n"); if (verbose < 2) return; - if (!config_fetch(d, where + 4, 4)) + if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) { printf("\t\t\n"); return; } - l1_cap = get_conf_long(d, where + 4); + l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); printf("\t\tL1SubCap: "); printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", - FLAG(l1_cap, 1), - FLAG(l1_cap, 2), - FLAG(l1_cap, 4), - FLAG(l1_cap, 8), - FLAG(l1_cap, 16)); - - if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1)) + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11), + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || + l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) { printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8,8)); - power_on_scale = BITS(l1_cap, 16, 2); + time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5)); + if (time != -1) + printf("PortTPowerOnTime=%dus\n", time); + else + printf("PortTPowerOnTime=\n"); + } - printf("PortTPowerOnTime="); - switch (power_on_scale) - { - case 0: - printf("%dus\n", BITS(l1_cap, 19, 5) * 2); - break; - case 1: - printf("%dus\n", BITS(l1_cap, 19, 5) * 10); - break; - case 2: - printf("%dus\n", BITS(l1_cap, 19, 5) * 100); - break; - default: - printf("\n"); - break; - } + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); + printf("\t\tL1SubCtl1: "); + printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n", + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12), + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || + l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + printf("\t\t\t T_CommonMode=%dus ", + BITS(val, 8,8)); + + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + scale = BITS(val, 29, 3); + if (scale > 5) + printf("LTR1.2_Threshhold=\n"); + else + printf("LTR1.2_Threshhold=%lldns\n", + BITS(val, 16, 10) * + (unsigned long long)cap_ltr_scale(scale)); + } + + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); + printf("\t\tL1SubCtl2: "); + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || + l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) + { + time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5)); + if (time != -1) + printf("T_PwrOn=%dus\n", time); + else + printf("T_PwrOn=\n"); } }