From patchwork Tue Sep 15 17:10:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wdavis@nvidia.com X-Patchwork-Id: 518030 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id CA4FC14018C for ; Wed, 16 Sep 2015 03:11:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751330AbbIORLY (ORCPT ); Tue, 15 Sep 2015 13:11:24 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7797 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751074AbbIORLX (ORCPT ); Tue, 15 Sep 2015 13:11:23 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 15 Sep 2015 10:11:30 -0700 Received: from HQMAIL107.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 15 Sep 2015 10:06:11 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 15 Sep 2015 10:06:11 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 15 Sep 2015 17:11:23 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 15 Sep 2015 17:11:22 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Tue, 15 Sep 2015 17:11:22 +0000 Received: from wdavis-lt.nvidia.com (Not Verified[10.20.168.59]) by hqnvemgw01.nvidia.com with MailMarshal (v7, 1, 2, 5326) id ; Tue, 15 Sep 2015 10:11:22 -0700 From: Will Davis To: Bjorn Helgaas CC: Alex Williamson , Joerg Roedel , , , Konrad Wilk , "Mark Hounschell" , "David S. Miller" , Jonathan Corbet , Terence Ripperda , John Hubbard , Jerome Glisse , "Will Davis" Subject: [PATCH 02/22] linux/types.h: Add dma_peer_addr_t type Date: Tue, 15 Sep 2015 12:10:47 -0500 Message-ID: <1442337067-22964-3-git-send-email-wdavis@nvidia.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1442337067-22964-1-git-send-email-wdavis@nvidia.com> References: <1442337067-22964-1-git-send-email-wdavis@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On some platforms, a dma_addr_t is only 32 bits wide, but the bus addresses can be 64 bits wide. For peer-to-peer DMA, a device needs to use the full 64-bit address. Therefore, introduce a DMA address type that is not constrained by the CPU DMA address size. This is only needed for peer-to-peer DMA, so guard this definition with a CONFIG_HAS_DMA_P2P check. Signed-off-by: Will Davis --- include/linux/types.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/include/linux/types.h b/include/linux/types.h index 8715287..dd85173 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -140,13 +140,13 @@ typedef unsigned long blkcnt_t; #define pgoff_t unsigned long /* - * A dma_addr_t can hold any valid DMA address, i.e., any address returned + * A dma_addr_t can hold any valid DMA address, i.e., most addresses returned * by the DMA API. * * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 * bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, - * so they don't care about the size of the actual bus addresses. + * so they don't care about the size of the actual bus addresses in most cases. */ #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT typedef u64 dma_addr_t; @@ -154,6 +154,15 @@ typedef u64 dma_addr_t; typedef u32 dma_addr_t; #endif +/* + * Unlike dma_addr_t, a dma_peer_addr_t can hold any bus address for the + * platform. Drivers should only need this for peer-to-peer use cases, where + * the DMA target is also on the bus. + */ +#ifdef CONFIG_HAS_DMA_P2P +typedef u64 dma_peer_addr_t; +#endif + typedef unsigned __bitwise__ gfp_t; typedef unsigned __bitwise__ fmode_t; typedef unsigned __bitwise__ oom_flags_t;