From patchwork Tue Aug 18 19:04:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wdavis@nvidia.com X-Patchwork-Id: 508441 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7A54A14030F for ; Wed, 19 Aug 2015 05:19:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753342AbbHRTTY (ORCPT ); Tue, 18 Aug 2015 15:19:24 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5889 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754100AbbHRTTU (ORCPT ); Tue, 18 Aug 2015 15:19:20 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 18 Aug 2015 12:18:32 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 18 Aug 2015 12:16:05 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 18 Aug 2015 12:16:05 -0700 Received: from HQPUB102.nvidia.com (172.18.146.14) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Tue, 18 Aug 2015 12:19:19 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQPUB102.nvidia.com (172.18.146.14) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 18 Aug 2015 19:19:19 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Tue, 18 Aug 2015 19:19:19 +0000 Received: from wdavis-lt.nvidia.com (Not Verified[10.20.168.59]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 18 Aug 2015 12:19:19 -0700 From: Will Davis To: Bjorn Helgaas CC: Alex Williamson , Joerg Roedel , , , Konrad Wilk , Mark Hounschell , "David S. Miller" , Jonathan Corbet , Terence Ripperda , John Hubbard , Jerome Glisse , Will Davis Subject: [PATCH v5 12/13] x86: add pci-nommu implementation of map_peer_resource Date: Tue, 18 Aug 2015 14:04:08 -0500 Message-ID: <1439924649-29698-13-git-send-email-wdavis@nvidia.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1439924649-29698-1-git-send-email-wdavis@nvidia.com> References: <1439924649-29698-1-git-send-email-wdavis@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add Intel nommu implementation of 'map_peer_resource', which simply checks whether peer traffic should be allowed and converts the resource to a bus address. Add behind CONFIG_HAS_DMA_P2P guards, since the dma_map_ops members are behind them as well. Signed-off-by: Will Davis --- arch/x86/kernel/pci-nommu.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c index da15918..4b45cc6 100644 --- a/arch/x86/kernel/pci-nommu.c +++ b/arch/x86/kernel/pci-nommu.c @@ -38,6 +38,39 @@ static dma_addr_t nommu_map_page(struct device *dev, struct page *page, return bus; } +#ifdef CONFIG_HAS_DMA_P2P +static dma_peer_addr_t nommu_map_peer_resource(struct device *dev, + struct device *peer, + struct resource *res, + unsigned long offset, + size_t size, + enum dma_data_direction dir, + struct dma_attrs *attrs) +{ + struct pci_dev *pdev; + struct pci_dev *ppeer; + struct pci_bus_region region; + dma_peer_addr_t dma_address; + + if (!dev_is_pci(dev) || !dev_is_pci(peer)) + return DMA_ERROR_CODE; + + pdev = to_pci_dev(dev); + ppeer = to_pci_dev(peer); + + if (!pci_peer_traffic_supported(pdev, ppeer)) + return DMA_ERROR_CODE; + + pcibios_resource_to_bus(pdev->bus, ®ion, res); + dma_address = region.start + offset; + WARN_ON(size == 0); + if (!check_addr("map_peer_resource", dev, dma_address, size)) + return DMA_ERROR_CODE; + flush_write_buffers(); + return dma_address; +} +#endif + /* Map a set of buffers described by scatterlist in streaming * mode for DMA. This is the scatter-gather version of the * above pci_map_single interface. Here the scatter gather list @@ -93,6 +126,9 @@ struct dma_map_ops nommu_dma_ops = { .free = dma_generic_free_coherent, .map_sg = nommu_map_sg, .map_page = nommu_map_page, +#ifdef CONFIG_HAS_DMA_P2P + .map_peer_resource = nommu_map_peer_resource, +#endif .sync_single_for_device = nommu_sync_single_for_device, .sync_sg_for_device = nommu_sync_sg_for_device, .is_phys = 1,