From patchwork Wed May 28 14:49:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 353487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4EF9E140082 for ; Thu, 29 May 2014 00:52:18 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754457AbaE1Ov5 (ORCPT ); Wed, 28 May 2014 10:51:57 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:43581 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753841AbaE1Ov4 (ORCPT ); Wed, 28 May 2014 10:51:56 -0400 Received: by mail-wi0-f174.google.com with SMTP id r20so3952814wiv.1 for ; Wed, 28 May 2014 07:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dbGV5c7DgmuscDLCqWF/hnfxY/oxWigfnbc1CWgmi7Y=; b=md5693afGTSA5l/E2e261emR5aKFyVr43PsnuUSCybjsiR4yF5ZwEUsB6FVP8r9/8P kM12/rTOp3rO+I742lH7V0JfFJe0RBxxoRvgbJy7+x/DF4QVfFDlcMPpvzhV7xt9mz2q PLvUjn3OnL3Lkw/g42xFkKzPm2Z26kD87PiT7LuIi6LHnvaxQ16xPx8i7+ZCx5mF0PR6 ONi/ILpyAMhd82S7n+MHbQG/pqNuyMgd+tX5gNAMm1Ubbw6Nt1+LpkhVoY6yD58lCuFP cNYSujyAjwFgDggxmivhiK3n4jnUABLZvkkm+HShgEaT6OoAxoZPPgtZZjrtzanjsBZW 8BJQ== X-Received: by 10.180.94.98 with SMTP id db2mr1552653wib.1.1401288711487; Wed, 28 May 2014 07:51:51 -0700 (PDT) Received: from localhost (port-91146.pppoe.wtnet.de. [84.46.68.127]) by mx.google.com with ESMTPSA id u1sm17464197wia.16.2014.05.28.07.51.50 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 May 2014 07:51:50 -0700 (PDT) From: Thierry Reding To: Stephen Warren , Bjorn Helgaas Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 1/5] PCI: tegra: Overhaul regulator usage Date: Wed, 28 May 2014 16:49:11 +0200 Message-Id: <1401288555-24197-2-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1401288555-24197-1-git-send-email-thierry.reding@gmail.com> References: <1401288555-24197-1-git-send-email-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thierry Reding The current usage of regulators for the Tegra PCIe block is wrong. It doesn't accurately reflect the actual supply inputs of the IP block and therefore isn't as flexible as it should be. Rectify this by describing all possible supply inputs in the device tree binding documentation and deprecate the old supply properties. Signed-off-by: Thierry Reding --- Changes in v2: - fix power rail assignment on Tegra30 .../bindings/pci/nvidia,tegra20-pcie.txt | 35 ++++++++++++++++++++-- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index c300391e8d3e..f56d89998a44 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -14,9 +14,6 @@ Required properties: - interrupt-names: Must include the following entries: "intr": The Tegra interrupt that is asserted for controller interrupts "msi": The Tegra interrupt that is asserted when an MSI is received -- pex-clk-supply: Supply voltage for internal reference clock -- vdd-supply: Power supply for controller (1.05V) -- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) - bus-range: Range of bus numbers associated with this controller - #address-cells: Address representation for root ports (must be 3) - cell 0 specifies the bus and device numbers of the root port: @@ -60,6 +57,38 @@ Required properties: - afi - pcie_x +Power supplies for Tegra20: +- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. +- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. +- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. +- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must + supply 1.05 V. +- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. + +Power supplies for Tegra30: +- Required: + - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must + supply 1.05 V. + - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must + supply 1.05 V. + - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must + supply 1.8 V. + - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. + Must supply 3.3 V. +- Optional: + - If lanes 0 to 3 are used: + - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + - If lanes 4 or 5 are used: + - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. + - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. + +Deprecated supplies: +- pex-clk-supply: Supply voltage for internal reference clock +- vdd-supply: Power supply for controller (1.05V) +- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) + Root ports are defined as subnodes of the PCIe controller node. Required properties: