From patchwork Thu Mar 27 09:26:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 334265 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 60B9E140088 for ; Thu, 27 Mar 2014 20:27:22 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754102AbaC0J1S (ORCPT ); Thu, 27 Mar 2014 05:27:18 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:36473 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754104AbaC0J1K (ORCPT ); Thu, 27 Mar 2014 05:27:10 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 27 Mar 2014 18:27:09 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 63CAF445ED; Thu, 27 Mar 2014 18:27:09 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id 5A58E280A5; Thu, 27 Mar 2014 18:27:09 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id 53D14280A0; Thu, 27 Mar 2014 18:27:09 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac2.idc.renesas.com with ESMTP id UAB11041; Thu, 27 Mar 2014 18:27:09 +0900 X-IronPort-AV: E=Sophos;i="4.97,741,1389711600"; d="scan'208";a="156440000" Received: from unknown (HELO relay41.aps.necel.com) ([10.29.19.9]) by relmlii1.idc.renesas.com with ESMTP; 27 Mar 2014 18:27:09 +0900 Received: from DU0NOTES13.ad.ree.renesas.com ([172.29.24.131]) by relay41.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id s2R9R33D015745; Thu, 27 Mar 2014 18:27:07 +0900 (JST) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by DU0NOTES13.ad.ree.renesas.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2014032710270149-166384 ; Thu, 27 Mar 2014 10:27:01 +0100 From: Phil Edworthy To: linux-pci@vger.kernel.org Cc: linux-sh@vger.kernel.org, LAKML , Bjorn Helgaas , Valentine Barshak , Simon Horman , Magnus Damm , Ben Dooks , Phil Edworthy X-Mailer: git-send-email 1.9.0 In-Reply-To: <1395912416-20087-1-git-send-email-phil.edworthy@renesas.com> References: <1395912416-20087-1-git-send-email-phil.edworthy@renesas.com> X-TNEFEvaluated: 1 Message-ID: <1395912416-20087-5-git-send-email-phil.edworthy@renesas.com> Date: Thu, 27 Mar 2014 09:26:50 +0000 Subject: [PATCH v6 04/10] ARM: shmobile: r8a7791: Add PCIe clock device tree nodes X-MIMETrack: Itemize by SMTP Server on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 27.03.2014 10:27:01, Serialize by Router on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 27.03.2014 10:27:08, Serialize complete at 27.03.2014 10:27:08 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch adds the device tree clock nodes for PCIe Signed-off-by: Phil Edworthy --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- include/dt-bindings/clock/r8a7791-clock.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 71bac2c..ccfba57 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -717,14 +717,17 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, - <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; + <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>, + <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 + R8A7791_CLK_PCIE >; clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1", + "pcie"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index 30f82f2..d3e2cf5 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -51,6 +51,7 @@ #define R8A7791_CLK_SDHI1 12 #define R8A7791_CLK_SDHI0 14 #define R8A7791_CLK_MMCIF0 15 +#define R8A7791_CLK_PCIE 19 #define R8A7791_CLK_SSUSB 28 #define R8A7791_CLK_CMT1 29 #define R8A7791_CLK_USBDMAC0 30