| Message ID | 1365000318-28256-10-git-send-email-thierry.reding@avionic-design.de |
|---|---|
| State | Not Applicable |
| Headers | show |
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 1ae37ba..e396cb2 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -64,6 +64,14 @@ }; }; + pcie-controller { + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + }; + sound { compatible = "ad,tegra-audio-wm8903-tec", "nvidia,tegra-audio-wm8903";
Enable the first PCIe root port which is connected to an FPGA on the Tamonten Evaluation Carrier and add device nodes for each of the PCI endpoints available in the standard configuration. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> --- Changes in v2: - remove duplicate nodes and properties defined in tegra20-tamonten.dtsi Changes in v3: - remove PCIe endpoint device tree nodes, all devices can be discovered via standard PCI enumeration arch/arm/boot/dts/tegra20-tec.dts | 8 ++++++++ 1 file changed, 8 insertions(+)