| Message ID | 1359399397-29729-25-git-send-email-thomas.petazzoni@free-electrons.com |
|---|---|
| State | Not Applicable |
| Headers | show |
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 8e53b25..7dcc36c 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -90,5 +90,32 @@ phy = <&phy3>; phy-mode = "sgmii"; }; + + pcie-controller { + status = "okay"; + + /* + * All 6 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@0,0 { + status = "okay"; + }; + pcie@0,1 { + status = "okay"; + }; + pcie@0,2 { + status = "okay"; + }; + pcie@0,3 { + status = "okay"; + }; + pcie@2,0 { + status = "okay"; + }; + pcie@3,0 { + status = "okay"; + }; + }; }; };
The Marvell evaluation board (DB) for the Armada XP SoC has 6 physicals full-size PCIe slots, so we enable the corresponding PCIe interfaces in the Device Tree. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- arch/arm/boot/dts/armada-xp-db.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)