From patchwork Wed Aug 1 15:54:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 174506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 501482C007F for ; Thu, 2 Aug 2012 02:03:58 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755858Ab2HAP4d (ORCPT ); Wed, 1 Aug 2012 11:56:33 -0400 Received: from mail-gh0-f174.google.com ([209.85.160.174]:57673 "EHLO mail-gh0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755809Ab2HAP42 (ORCPT ); Wed, 1 Aug 2012 11:56:28 -0400 Received: by mail-gh0-f174.google.com with SMTP id r11so984595ghr.19 for ; Wed, 01 Aug 2012 08:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=No04vJFffkgkNugNvL+ZijKQzQzScZBAj9f1jH+u0Fo=; b=D9Up6dXxAdjwus0KRb9JS2us4XemSOj2tXQCClw/dFLbb+/xmTBzkPQmowaVFLe5Ry PsB6Ga1ENmSmdOc+8n1v9GNEntfzRckN3OTKFD4xuaUVmPiV4FczL6dybJtzinW7Sb+f 9QpawZrNiUJQY4pJqen1vW2ACfbHRw25/YPjxScRtZewDC7bnyBZ7zo9co5DyZ0DaBdB 7gJxpcfG/SHOY1+NiY93Pnuc+qOfyjR0EUFdbbQlEHx/0UPCNBRo+71+JOHlVHoOK8Ji D5n/kasfJT9vJQa7pHmYf60f+haLikbW/qV1u02dd0jOQe+/6WnRD6RRoxo/FA8V4VdS 2jiA== Received: by 10.66.74.195 with SMTP id w3mr40742041pav.64.1343836587794; Wed, 01 Aug 2012 08:56:27 -0700 (PDT) Received: from localhost.localdomain ([58.250.81.2]) by mx.google.com with ESMTPS id pe8sm2816231pbc.76.2012.08.01.08.56.20 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Aug 2012 08:56:27 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [PATCH v3 08/32] PCI/pciehp: use PCIe capabilities access functions to simplify implementation Date: Wed, 1 Aug 2012 23:54:13 +0800 Message-Id: <1343836477-7287-9-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify pciehp implementation. Signed-off-by: Jiang Liu Signed-off-by: Yijing Wang Reviewed-by: Kenji Kaneshige --- drivers/pci/hotplug/pciehp_acpi.c | 6 +----- drivers/pci/hotplug/pciehp_hpc.c | 12 ++++-------- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_acpi.c b/drivers/pci/hotplug/pciehp_acpi.c index 376d70d..751b41c 100644 --- a/drivers/pci/hotplug/pciehp_acpi.c +++ b/drivers/pci/hotplug/pciehp_acpi.c @@ -81,16 +81,12 @@ static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots); /* Dummy driver for dumplicate name detection */ static int __init dummy_probe(struct pcie_device *dev) { - int pos; u32 slot_cap; acpi_handle handle; struct dummy_slot *slot, *tmp; struct pci_dev *pdev = dev->port; - pos = pci_pcie_cap(pdev); - if (!pos) - return -ENODEV; - pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap); + pci_pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); slot = kzalloc(sizeof(*slot), GFP_KERNEL); if (!slot) return -ENOMEM; diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 302451e..cf0daf1 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -44,25 +44,25 @@ static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) { struct pci_dev *dev = ctrl->pcie->port; - return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); + return pci_pcie_capability_read_word(dev, reg, value); } static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) { struct pci_dev *dev = ctrl->pcie->port; - return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); + return pci_pcie_capability_read_dword(dev, reg, value); } static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) { struct pci_dev *dev = ctrl->pcie->port; - return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); + return pci_pcie_capability_write_word(dev, reg, value); } static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) { struct pci_dev *dev = ctrl->pcie->port; - return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); + return pci_pcie_capability_write_dword(dev, reg, value); } /* Power Control Command */ @@ -855,10 +855,6 @@ struct controller *pcie_init(struct pcie_device *dev) goto abort; } ctrl->pcie = dev; - if (!pci_pcie_cap(pdev)) { - ctrl_err(ctrl, "Cannot find PCI Express capability\n"); - goto abort_ctrl; - } if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); goto abort_ctrl;