From patchwork Wed Aug 1 15:54:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 174487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A50842C008B for ; Thu, 2 Aug 2012 02:01:10 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756155Ab2HAQAY (ORCPT ); Wed, 1 Aug 2012 12:00:24 -0400 Received: from mail-gg0-f174.google.com ([209.85.161.174]:40535 "EHLO mail-gg0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756147Ab2HAQAW (ORCPT ); Wed, 1 Aug 2012 12:00:22 -0400 Received: by ggnl2 with SMTP id l2so181856ggn.19 for ; Wed, 01 Aug 2012 09:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=VOMi0MnDBLpwEaQZ1FCvM+mgx1NgFkz/4vLxpavQWyA=; b=NrzUxquYRKsF+r2iXaGNuKdIVG7XRHcNG+CieM1lKiew8zrFtr8U7itEgUfFof8lv/ L4UxS5Zi3WwCtwJKSj+8l2s5d/5AnAkSAebsn+NKSMZhZqsOPi+LExqAWIxeMYu8eyej yZSH5eCqkd2hRUSOWfIrb5Qn8Cy3fAW1Ch8mZ++lApe5PuJD6hjX50MK6zgq12PlZ/Uu W3Ayp9xUUJjrGtZeq+mwFZJa1b8Zfp/VHThACeCFdrIhJAuh6TMQb7KBANHiX6MtZyXO UcQUND7NdOwBxFAWmoJ822onMSp3Cev3D3aXXKC2eEMADfTnhVk4OorjeQEyNX0QzbbK fobA== Received: by 10.66.76.196 with SMTP id m4mr40961810paw.61.1343836821385; Wed, 01 Aug 2012 09:00:21 -0700 (PDT) Received: from localhost.localdomain ([58.250.81.2]) by mx.google.com with ESMTPS id pe8sm2816231pbc.76.2012.08.01.09.00.12 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Aug 2012 09:00:20 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile , Mark Einon Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [PATCH v3 31/32] PCI/et131x: use PCIe capabilities access functions to simplify implementation Date: Wed, 1 Aug 2012 23:54:36 +0800 Message-Id: <1343836477-7287-32-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> References: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify et131x driver's implementation. Signed-off-by: Jiang Liu --- drivers/staging/et131x/et131x.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c index 5b11c5e..7c2e781 100644 --- a/drivers/staging/et131x/et131x.c +++ b/drivers/staging/et131x/et131x.c @@ -4001,16 +4001,14 @@ static void et131x_hwaddr_init(struct et131x_adapter *adapter) static int et131x_pci_init(struct et131x_adapter *adapter, struct pci_dev *pdev) { - int cap = pci_pcie_cap(pdev); u16 max_payload; - u16 ctl; int i, rc; rc = et131x_init_eeprom(adapter); if (rc < 0) goto out; - if (!cap) { + if (!pci_is_pcie(pdev)) { dev_err(&pdev->dev, "Missing PCIe capabilities\n"); goto err_out; } @@ -4018,7 +4016,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter, /* Let's set up the PORT LOGIC Register. First we need to know what * the max_payload_size is */ - if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCAP, &max_payload)) { + if (pci_pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) { dev_err(&pdev->dev, "Could not read PCI config space for Max Payload Size\n"); goto err_out; @@ -4055,17 +4053,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter, } /* Change the max read size to 2k */ - if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl)) { + if (pci_pcie_capability_change_word(pdev, PCI_EXP_DEVCTL, + 0x4 << 12, PCI_EXP_DEVCTL_READRQ)) { dev_err(&pdev->dev, - "Could not read PCI config space for Max read size\n"); - goto err_out; - } - - ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | (0x04 << 12); - - if (pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl)) { - dev_err(&pdev->dev, - "Could not write PCI config space for Max read size\n"); + "Couldn't change PCI config space for Max read size\n"); goto err_out; }