From patchwork Tue Jul 24 16:41:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 172960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 829142C007F for ; Wed, 25 Jul 2012 02:45:10 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754743Ab2GXQoY (ORCPT ); Tue, 24 Jul 2012 12:44:24 -0400 Received: from mail-gh0-f174.google.com ([209.85.160.174]:58608 "EHLO mail-gh0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753864Ab2GXQoW (ORCPT ); Tue, 24 Jul 2012 12:44:22 -0400 Received: by ghrr11 with SMTP id r11so6863911ghr.19 for ; Tue, 24 Jul 2012 09:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=ILXlhSZ05XiTJXzKfeKVvCfJ+Si29rvYd1E4IrjOo3U=; b=n1bL16q+8c0LlR2oGRGHH+02nPSiCs/NgnLUHrMHF/8sFmcZJA6x6r8Ko0HP2/g8QH fnM/8SMerAl8PV1L+TiBwMa2YyHriv4IeeYiyZZkGpqrGbPYDUnUONxTm6jAxA91BRb0 lq9g0PTaQsLxQ0dQm/O6Hv4lUUJ/ABQw15f93NOjJ7Yg8cpb18RFO+0JUSXmZNZ6+CjU /E8DMBltkleT2hHJUI8jYcpVvp0UBvgTQ0izt41CPDu0wkTuLopvY8wKxjtCD/QC3jTm K05+7mDEpw2ZQtbE/M4Aa0G5/rJzKMQjh5SsfNtsIkTB5+jd6h85ecSAu5li/Z7WB1cR vd/g== Received: by 10.66.75.202 with SMTP id e10mr6017232paw.55.1343148260978; Tue, 24 Jul 2012 09:44:20 -0700 (PDT) Received: from localhost.localdomain ([221.221.26.244]) by mx.google.com with ESMTPS id wk10sm7863878pbc.71.2012.07.24.09.44.10 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 09:44:17 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH v2 30/32] PCI/tsi721: use PCIe capabilities access functions to simplify implementation Date: Wed, 25 Jul 2012 00:41:15 +0800 Message-Id: <1343148077-25941-7-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343148077-25941-1-git-send-email-jiang.liu@huawei.com> References: <1343148077-25941-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify tsi721 driver's implementation. Signed-off-by: Jiang Liu --- drivers/rapidio/devices/tsi721.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c index 722246c..4debfdc 100644 --- a/drivers/rapidio/devices/tsi721.c +++ b/drivers/rapidio/devices/tsi721.c @@ -2212,7 +2212,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct tsi721_device *priv; - int i, cap; + int i; int err; u32 regval; @@ -2320,20 +2320,19 @@ static int __devinit tsi721_probe(struct pci_dev *pdev, dev_info(&pdev->dev, "Unable to set consistent DMA mask\n"); } - cap = pci_pcie_cap(pdev); - BUG_ON(cap == 0); + BUG_ON(!pci_is_pcie(pdev)); /* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */ - pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, ®val); + pci_pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL, ®val); regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN); regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT; - pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval); + pci_pcie_capability_write_dword(pdev, PCI_EXP_DEVCTL, regval); /* Adjust PCIe completion timeout. */ - pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, ®val); + pci_pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL2, ®val); regval &= ~(0x0f); - pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2); + pci_pcie_capability_write_dword(pdev, PCI_EXP_DEVCTL2, regval | 0x2); /* * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block