From patchwork Fri Jun 8 10:00:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 163741 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 71901B6FD5 for ; Fri, 8 Jun 2012 19:58:32 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932554Ab2FHJ6b (ORCPT ); Fri, 8 Jun 2012 05:58:31 -0400 Received: from mga01.intel.com ([192.55.52.88]:12344 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762050Ab2FHJ6a (ORCPT ); Fri, 8 Jun 2012 05:58:30 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 08 Jun 2012 02:58:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="162773598" Received: from lahna.fi.intel.com ([10.237.72.174]) by fmsmga001.fm.intel.com with ESMTP; 08 Jun 2012 02:58:25 -0700 Received: from westeri by lahna.fi.intel.com with local (Exim 4.77) (envelope-from ) id 1ScvzB-0001W0-19; Fri, 08 Jun 2012 13:00:05 +0300 From: Mika Westerberg To: linux-pci@vger.kernel.org Cc: mj@ucw.cz, Mika Westerberg Subject: [PCIUTILS PATCH] Display whether LTR/OBFF are supported and enabled Date: Fri, 8 Jun 2012 13:00:04 +0300 Message-Id: <1339149604-5653-1-git-send-email-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 1.7.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DEVCAP2 and DEVCTL2 capabilities contain information whether LTR and OBFF are supported and enabled. Make sure this is displayed to user as well. Signed-off-by: Mika Westerberg --- lib/header.h | 4 ++++ ls-caps.c | 44 ++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 44 insertions(+), 4 deletions(-) diff --git a/lib/header.h b/lib/header.h index 85b8b9f..b418982 100644 --- a/lib/header.h +++ b/lib/header.h @@ -845,11 +845,15 @@ #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ #define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */ +#define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */ +#define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported */ #define PCI_EXP_DEVCTL2 0x28 /* Device Control */ #define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */ #define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */ #define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */ #define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */ +#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */ +#define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ diff --git a/ls-caps.c b/ls-caps.c index 4a75ce7..0f6fab3 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -920,24 +920,60 @@ static const char *cap_express_dev2_timeout_value(int type) } } +static const char *cap_express_devcap2_obff(int obff) +{ + switch (obff) + { + case 1: + return "Via message"; + case 2: + return "Via WAKE#"; + case 3: + return "Via message/WAKE#"; + default: + return "Not Supported"; + } +} + +static const char *cap_express_devctl2_obff(int obff) +{ + switch (obff) + { + case 0: + return "Disabled"; + case 1: + return "Via message A"; + case 2: + return "Via message B"; + case 3: + return "Via WAKE#"; + default: + return "Unknown"; + } +} + static void cap_express_dev2(struct device *d, int where, int type) { u32 l; u16 w; l = get_conf_long(d, where + PCI_EXP_DEVCAP2); - printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c", + printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)), - FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS)); + FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS), + FLAG(l, PCI_EXP_DEVCAP2_LTR), + cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l))); if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI)); else printf("\n"); w = get_conf_word(d, where + PCI_EXP_DEVCTL2); - printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c", + printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s", cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)), - FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS)); + FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS), + FLAG(w, PCI_EXP_DEV2_LTR), + cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w))); if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM) printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI)); else