Show patches with: Submitter = Dan Williams       |    State = Action Required       |    Archived = No       |   248 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[GIT,PULL] Compute Express Linux (CXL) for v5.12-rc1 [GIT,PULL] Compute Express Linux (CXL) for v5.12-rc1 - - 6 - --- 2021-02-24 Dan Williams New
[1/8] cxl/mem: Move some definitions to mem.h CXL Port Enumeration - - 1 - --- 2021-03-24 Dan Williams New
[2/8] cxl/mem: Introduce 'struct cxl_regs' CXL Port Enumeration - - 2 - --- 2021-03-24 Dan Williams New
[3/8] cxl/core: Rename bus.c to core.c CXL Port Enumeration 1 - - - --- 2021-03-24 Dan Williams New
[4/8] cxl/core: Refactor CXL register lookup for bridge reuse CXL Port Enumeration - - 1 - --- 2021-03-24 Dan Williams New
[5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root CXL Port Enumeration - - - - --- 2021-03-24 Dan Williams New
[6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS CXL Port Enumeration 1 - - - --- 2021-03-24 Dan Williams New
[7/8] cxl/port: Introduce cxl_port objects CXL Port Enumeration - - - - --- 2021-03-24 Dan Williams New
[8/8] cxl/acpi: Add module parameters to stand in for ACPI tables CXL Port Enumeration - - - - --- 2021-03-24 Dan Williams New
PCI: Allow drivers to claim exclusive access to config regions PCI: Allow drivers to claim exclusive access to config regions - - - - --- 2021-03-25 Dan Williams New
[v2,1/8] cxl/mem: Move some definitions to mem.h CXL Port Enumeration - - 1 - --- 2021-04-01 Dan Williams New
[v2,2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices CXL Port Enumeration - - 1 - --- 2021-04-01 Dan Williams New
[v2,3/8] cxl/core: Rename bus.c to core.c CXL Port Enumeration 1 - - - --- 2021-04-01 Dan Williams New
[v2,4/8] cxl/core: Refactor CXL register lookup for bridge reuse CXL Port Enumeration - - 2 - --- 2021-04-01 Dan Williams New
[v2,5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root CXL Port Enumeration - - - - --- 2021-04-01 Dan Williams New
[v2,6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS CXL Port Enumeration 1 - - - --- 2021-04-01 Dan Williams New
[v2,7/8] cxl/port: Introduce cxl_port objects CXL Port Enumeration - - - - --- 2021-04-01 Dan Williams New
[v2,8/8] cxl/acpi: Add module parameters to stand in for ACPI tables CXL Port Enumeration - - - - --- 2021-04-01 Dan Williams New
[1/8] cxl/mem: Move some definitions to mem.h CXL Port Enumeration and Plans for v5.14 - - 2 - --- 2021-05-07 Dan Williams New
[2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices CXL Port Enumeration and Plans for v5.14 - - 2 - --- 2021-05-07 Dan Williams New
[3/8] cxl/core: Rename bus.c to core.c CXL Port Enumeration and Plans for v5.14 1 - 1 - --- 2021-05-07 Dan Williams New
[4/8] cxl/core: Refactor CXL register lookup for bridge reuse CXL Port Enumeration and Plans for v5.14 - - 2 - --- 2021-05-07 Dan Williams New
[5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root CXL Port Enumeration and Plans for v5.14 - - - - --- 2021-05-07 Dan Williams New
[6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS CXL Port Enumeration and Plans for v5.14 2 - - - --- 2021-05-07 Dan Williams New
[7/8] cxl/port: Introduce cxl_port objects CXL Port Enumeration and Plans for v5.14 - - 1 - --- 2021-05-07 Dan Williams New
[8/8] cxl/acpi: Add module parameters to stand in for ACPI tables CXL Port Enumeration and Plans for v5.14 - - - - --- 2021-05-07 Dan Williams New
[v4,1/8] cxl/mem: Move some definitions to mem.h CXL Port Enumeration and Plans for v5.14 - - 2 - --- 2021-05-14 Dan Williams New
[v4,2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices CXL Port Enumeration and Plans for v5.14 - - 2 - --- 2021-05-14 Dan Williams New
[v4,3/8] cxl/core: Rename bus.c to core.c CXL Port Enumeration and Plans for v5.14 1 - 1 - --- 2021-05-14 Dan Williams New
[v4,4/8] cxl/core: Refactor CXL register lookup for bridge reuse CXL Port Enumeration and Plans for v5.14 - - 2 - --- 2021-05-14 Dan Williams New
[v4,5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root CXL Port Enumeration and Plans for v5.14 - - 1 - --- 2021-05-14 Dan Williams New
[v4,6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS CXL Port Enumeration and Plans for v5.14 2 - - - --- 2021-05-14 Dan Williams New
[v4,7/8] cxl/port: Introduce cxl_port objects CXL Port Enumeration and Plans for v5.14 - - 1 - --- 2021-05-14 Dan Williams New
[v4,8/8] cxl/acpi: Add module parameters to stand in for ACPI tables CXL Port Enumeration and Plans for v5.14 - - - - --- 2021-05-14 Dan Williams New
[v5,5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Untitled series #243870 - - 1 - --- 2021-05-14 Dan Williams New
[v5,7/8] cxl/port: Introduce cxl_port objects Untitled series #243891 - - 1 - --- 2021-05-14 Dan Williams New
[v5,1/6] cxl/acpi: Local definition of ACPICA infrastructure CXL port and decoder enumeration - - - - --- 2021-06-06 Dan Williams New
[v5,2/6] cxl/acpi: Introduce cxl_root, the root of a cxl_port topology CXL port and decoder enumeration 1 - 1 - --- 2021-06-06 Dan Williams New
[v5,3/6] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS CXL port and decoder enumeration 2 - - - --- 2021-06-06 Dan Williams New
[v5,4/6] cxl/acpi: Add downstream port data to cxl_port instances CXL port and decoder enumeration - - - - --- 2021-06-06 Dan Williams New
[v5,5/6] cxl/acpi: Enumerate host bridge root ports CXL port and decoder enumeration - - 1 - --- 2021-06-06 Dan Williams New
[v5,6/6] cxl/acpi: Introduce cxl_decoder objects CXL port and decoder enumeration - - 1 - --- 2021-06-06 Dan Williams New
[v6,1/5] cxl/acpi: Introduce the root of a cxl_port topology CXL port and decoder enumeration 1 - 1 - --- 2021-06-09 Dan Williams New
[v6,2/5] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS CXL port and decoder enumeration 2 - - - --- 2021-06-09 Dan Williams New
[v6,3/5] cxl/acpi: Add downstream port data to cxl_port instances CXL port and decoder enumeration - - 2 - --- 2021-06-09 Dan Williams New
[v6,4/5] cxl/acpi: Enumerate host bridge root ports CXL port and decoder enumeration - - 1 - --- 2021-06-09 Dan Williams New
[v6,5/5] cxl/acpi: Introduce cxl_decoder objects CXL port and decoder enumeration - - 1 - --- 2021-06-09 Dan Williams New
[v7,5/5] cxl/acpi: Introduce cxl_decoder objects Untitled series #247983 - - 1 - --- 2021-06-09 Dan Williams New
[GIT,PULL] Compute Express Link (CXL) update for v5.14 [GIT,PULL] Compute Express Link (CXL) update for v5.14 - - - - --- 2021-07-03 Dan Williams New
[v3,01/10] cxl/pci: Convert register block identifiers to an enum cxl_pci refactor for reusability - - - - --- 2021-10-09 Dan Williams New
[v3,02/10] cxl/pci: Remove dev_dbg for unknown register blocks cxl_pci refactor for reusability - - - - --- 2021-10-09 Dan Williams New
[v3,03/10] cxl/pci: Fix NULL vs ERR_PTR confusion cxl_pci refactor for reusability - 1 2 - --- 2021-10-09 Dan Williams New
[v3,04/10] cxl/pci: Remove pci request/release regions cxl_pci refactor for reusability - - - - --- 2021-10-09 Dan Williams New
[v3,05/10] cxl/pci: Make more use of cxl_register_map cxl_pci refactor for reusability - - - - --- 2021-10-09 Dan Williams New
[v3,06/10] cxl/pci: Add @base to cxl_register_map cxl_pci refactor for reusability - - 1 - --- 2021-10-09 Dan Williams New
[v3,07/10] cxl/pci: Split cxl_pci_setup_regs() cxl_pci refactor for reusability - - 2 - --- 2021-10-09 Dan Williams New
[v3,08/10] PCI: Add pci_find_dvsec_capability to find designated VSEC cxl_pci refactor for reusability 1 - 3 1 --- 2021-10-09 Dan Williams New
[v3,09/10] cxl/pci: Use pci core's DVSEC functionality cxl_pci refactor for reusability - - 1 - --- 2021-10-09 Dan Williams New
[v3,10/10] ocxl: Use pci core's DVSEC functionality cxl_pci refactor for reusability 1 - 1 - --- 2021-10-09 Dan Williams New
[v4,05/10] cxl/pci: Make more use of cxl_register_map Untitled series #266232 - - 1 - --- 2021-10-09 Dan Williams New
[v5,05/10] cxl/pci: Make more use of cxl_register_map Untitled series #266924 - - 1 - --- 2021-10-13 Dan Williams New
[v5,06/10] cxl/pci: Add @base to cxl_register_map Untitled series #266924 - - 1 - --- 2021-10-13 Dan Williams New
[v6,03/10] cxl/pci: Fix NULL vs ERR_PTR confusion Untitled series #267396 - 1 2 - --- 2021-10-15 Dan Williams New
[v6,06/10] cxl/pci: Add @base to cxl_register_map Untitled series #267398 - - 2 - --- 2021-10-15 Dan Williams New
[v6,07/10] cxl/pci: Split cxl_pci_setup_regs() Untitled series #267406 - - 2 - --- 2021-10-15 Dan Williams New
[GIT,PULL] Compute Express Link update for v5.16 [GIT,PULL] Compute Express Link update for v5.16 - - - - --- 2021-11-05 Dan Williams New
[v3,01/40] cxl: Rename CXL_MEM to CXL_PCI CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,02/40] cxl/pci: Implement Interface Ready Timeout CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,03/40] cxl/pci: Defer mailbox status checks to command timeouts CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,04/40] cxl: Flesh out register names CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,05/40] cxl/pci: Add new DVSEC definitions CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,06/40] cxl/acpi: Map component registers for Root Ports CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,07/40] cxl: Introduce module_cxl_driver CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,08/40] cxl/core/port: Rename bus.c to port.c CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,09/40] cxl/decoder: Hide physical address information from non-root CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,10/40] cxl/core: Convert decoder range to resource CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,11/40] cxl/core/port: Clarify decoder creation CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,12/40] cxl/core: Fix cxl_probe_component_regs() error message CXL.mem Topology Discovery and Hotplug Support 1 1 1 - --- 2022-01-24 Dan Williams New
[v3,13/40] cxl/core/port: Make passthrough decoder init implicit CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,14/40] cxl/core: Track port depth CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,15/40] cxl: Prove CXL locking CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,16/40] cxl/core/port: Use dedicated lock for decoder target list CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,17/40] cxl/port: Introduce cxl_port_to_pci_bus() CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,18/40] cxl/pmem: Introduce a find_cxl_root() helper CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,19/40] cxl/port: Up-level cxl_add_dport() locking requirements to the caller CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,20/40] cxl/pci: Rename pci.h to cxlpci.h CXL.mem Topology Discovery and Hotplug Support 1 - 1 - --- 2022-01-24 Dan Williams New
[v3,21/40] cxl/core: Generalize dport enumeration in the core CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,22/40] cxl/core/hdm: Add CXL standard decoder enumeration to the core CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,23/40] cxl/core: Emit modalias for CXL devices CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,24/40] cxl/port: Add a driver for 'struct cxl_port' objects CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,25/40] cxl/core/port: Remove @host argument for dport + decoder enumeration CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
[v3,26/40] cxl/pci: Store component register base in cxlds CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,27/40] cxl/pci: Cache device DVSEC offset CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,28/40] cxl/pci: Retrieve CXL DVSEC memory info CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,29/40] cxl/pci: Implement wait for media active CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,30/40] cxl/pci: Emit device serial number CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,31/40] cxl/memdev: Add numa_node attribute CXL.mem Topology Discovery and Hotplug Support - - 1 - --- 2022-01-24 Dan Williams New
[v3,32/40] cxl/core/port: Add switch port enumeration CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,33/40] cxl/mem: Add the cxl_mem driver CXL.mem Topology Discovery and Hotplug Support - - - - --- 2022-01-24 Dan Williams New
[v3,34/40] cxl/core: Move target_list out of base decoder attributes CXL.mem Topology Discovery and Hotplug Support - - 2 - --- 2022-01-24 Dan Williams New
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