mbox series

[0/9] Add CXL 2.0 DVSEC Decoding

Message ID 20210604190541.175602-1-ben.widawsky@intel.com
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Series Add CXL 2.0 DVSEC Decoding | expand

Message

Ben Widawsky June 4, 2021, 7:05 p.m. UTC 
This series improves decoding of CXL 2.0 DVSEC registers by adding more DVSEC
identifiers and adding fields for the existing decoded identifier. Not all DVSEC
fields from 2.0 spec are enabled here, only enough for what we needed in driver
bring-up. The restructuring of the code does make it easy to add support for the
remaining fields. I submitted a PR for this on github a few months ago [1]. The
spec is available for download [2].

Breakdown of patches:
1-5: Rework existing decoding to support more DVSEC IDs
6: Improve CXL Device Decoding (8.1.3 from CXL 2.0 spec)
7: Add port capabilities (8.1.5 from CXL 2.0 spec)
8: Add register locator (8.1.9 from CXL 2.0 spec)
9: Report undecoded DVSECs

Here is an example decoded output of a 5.12 based kernel running in QEMU
emulation [3]

36:00.0 Memory controller [0502]: Intel Corporation Device 0d93 (rev 01) (prog-if 10)
	Subsystem: Red Hat, Inc. Device 1100

	<...>

	Capabilities: [100 v1] Designated Vendor-Specific: Vendor=1e98 ID=0000 Rev=1 Len=56: CXL
		CXLCap:	Cache- IO+ Mem+ Mem HW Init+ HDMCount 1 Viral-
		CXLCtl:	Cache- IO+ Mem+ Cache SF Cov 0 Cache SF Gran 0 Cache Clean- Viral-
		CXLSta:	Viral-
		CXLSta2:	ResetComplete+ ResetError- PMComplete-
		Cache Size Not Reported
		Range1: 10000000-fffffff
			Valid+ Active+ Type=CDAT Class=CDAT interleave=0 timeout=1s
		Range2: 0-ffffffffffffffff
			Valid- Active- Type=Volatile Class=DRAM interleave=0 timeout=1s
	Capabilities: [138 v1] Designated Vendor-Specific: Vendor=1e98 ID=0008 Rev=0 Len=36: CXL
		Block2	BIR: bar0	ID: component registers
			RegisterOffset: 0000000000000000
		Block3	BIR: bar2	ID: CXL device registers
			RegisterOffset: 0000000000000000
	Kernel driver in use: cxl_pci

Ben Widawsky (9):
  cxl: Rename variable to match other code
  cxl: Make id check more explicit
  cxl: Collect all DVSEC Device fields
  cxl: Rework caps to new function
  cxl: Rename caps to be device caps
  cxl: Implement more device DVSEC decoding
  cxl: Add support for DVSEC port cap
  cxl: Add DVSEC Register Locator
  cxl: Add placeholder for undecoded DVSECs

 lib/header.h |  78 ++++++++++++++-----
 ls-ecaps.c   | 206 ++++++++++++++++++++++++++++++++++++++++++++++-----
 2 files changed, 249 insertions(+), 35 deletions(-)

[1]: https://github.com/pciutils/pciutils/pull/59
[2]: https://www.computeexpresslink.org/download-the-specification
[3]: https://gitlab.com/bwidawsk/qemu