@@ -30,6 +30,12 @@
#define NAND_STOP_DELAY (2 * HZ/50)
#define PAGE_CHUNK_SIZE (2048)
#define BCH_THRESHOLD (8)
+#undef PXA3XX_NAND_DEBUG
+#ifdef PXA3XX_NAND_DEBUG
+#define DBG_NAND(x) do{x;}while(0)
+#else
+#define DBG_NAND(x)
+#endif
/* registers and bit definitions */
#define NDCR (0x00) /* Control register */
@@ -411,6 +417,8 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
}
/* clear status bits and run */
+ DBG_NAND(printk("@@@ndcr set: %x, ndeccctrl set %x\n",
+ ndcr, ndeccctrl));
nand_writel(nand, NDCR, 0);
nand_writel(nand, NDECCCTRL, ndeccctrl);
nand_writel(nand, NDSR, NDSR_MASK);
@@ -456,6 +464,8 @@ static void handle_data_pio(struct pxa3xx_nand *nand)
{
struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+ DBG_NAND(printk("data size %x, oob size %x\n",
+ nand->data_size, nand->oob_size));
if (nand->state & STATE_IS_WRITE) {
__raw_writesl(nand->mmio_base + NDDB, info->data_buff,
DIV_ROUND_UP(nand->data_size, 4));
@@ -492,6 +502,8 @@ static void start_data_dma(struct pxa3xx_nand
*nand, int dir_out)
desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
}
+ DBG_NAND(printk("DMA START:DMA dcmd %x, dsadr %x, dtadr %x, len %x\n",
+ desc->dcmd, desc->dsadr, desc->dtadr, dma_len));
DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
DDADR(info->data_dma_ch) = info->data_desc_addr;