b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -17,6 +17,7 @@
* enable such tuning for those platform which support it */
#define PXA3XX_ADV_TIME_TUNING (1 << 4)
#define PXA3XX_KEEP_CONFIG (1 << 5)
+#define PXA3XX_POOLING_MODE (1 << 6)
struct pxa3xx_nand_platform_data {
unsigned int controller_attrs;
const struct mtd_partition *parts[NUM_CHIP_SELECT];
@@ -274,6 +274,10 @@ static int use_dma = 1;
module_param(use_dma, bool, 0444);
MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
+static int use_polling = 0;
+module_param(use_polling, bool, 0444);
+MODULE_PARM_DESC(use_polling, "Use full polling mode");
+
const static struct pxa3xx_nand_cmdset cmdset = {
.read1 = 0x3000,
.read2 = 0x0050,
@@ -444,6 +448,7 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
info = nand->info[nand->chip_select];
ndcr = info->reg_ndcr;
ndcr |= nand->use_dma ? NDCR_DMA_EN : 0;
+ ndcr |= use_polling ? NDCR_INT_MASK : 0;
ndcr |= NDCR_ND_RUN;
switch (nand->ecc_strength) {
@@ -615,9 +620,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
}
-static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
+static int pxa3xx_nand_transaction(struct pxa3xx_nand *nand)
{
- struct pxa3xx_nand *nand = devid;
struct pxa3xx_nand_info *info;
unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;