From patchwork Wed Jul 28 05:57:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 60096 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E73BE1007D2 for ; Wed, 28 Jul 2010 16:00:51 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OdzfA-0004bW-Gn; Wed, 28 Jul 2010 05:58:44 +0000 Received: from mail-px0-f177.google.com ([209.85.212.177]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Odzdf-0002n7-E7; Wed, 28 Jul 2010 05:57:12 +0000 Received: by mail-px0-f177.google.com with SMTP id 13so924820pxi.36 for ; Tue, 27 Jul 2010 22:57:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=uNAO1hb675HIG9tfb2kWxqUpeSZ2ufI9gcZAs6vPW9c=; b=Hhgq5cqBG5k1S1dG5wLx8WgQ7vae/Jehz26qmkYPu2rnLt7X7Uxu+z2wb1H20UgGL5 /Lix38EYXGb5NclNIPN3BN0gMWc8yvF/W34A//3IJsjSH6Q+CcLPPa+awrcmhkNDeHhG 50JAX6bxLKEPOFnfE3+glhi6eq0OXYOlP4d+g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=X8QZr+4XgsJIOwxEvFhXx+qn36ea1fNUPHIMI/zB4b2stMCvWHWeRZvg1+QY7Yyuoy CAr15C34XLCoFLBCFfVytPynZUmJJAr43Gumzv6fNyfZxREoU6CxOTTDXx1XlG9RxDgN efcqlzIlQmIxsi+9be85JZHjtjb0cl5Zy2vhs= MIME-Version: 1.0 Received: by 10.142.210.2 with SMTP id i2mr11287864wfg.173.1280296630374; Tue, 27 Jul 2010 22:57:10 -0700 (PDT) Received: by 10.142.54.6 with HTTP; Tue, 27 Jul 2010 22:57:10 -0700 (PDT) Date: Wed, 28 Jul 2010 13:57:10 +0800 Message-ID: Subject: [PATCH 12/29] pxa3xx_nand: clean the keep configure code From: Haojian Zhuang To: Eric Miao , linux-arm-kernel , David Woodhouse , David Woodhouse , Marc Kleine-Budde , linux-mtd@lists.infradead.org, Lei Wen X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100728_015711_858855_9597E42A X-CRM114-Status: GOOD ( 22.30 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (haojian.zhuang[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From b4c1fcd15307a86088ba7220d12979fe91909c9b Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Tue, 22 Jun 2010 21:41:47 +0800 Subject: [PATCH 12/29] pxa3xx_nand: clean the keep configure code Signed-off-by: Lei Wen --- arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | 1 + drivers/mtd/nand/pxa3xx_nand.c | 107 +++++++++----------------- 2 files changed, 38 insertions(+), 70 deletions(-) static const char *mtd_names[] = {"pxa3xx_nand-0", NULL}; @@ -758,7 +758,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, /* calculate flash information */ info->cmdset = f->cmdset; info->page_size = f->page_size; - info->oob_buff = info->data_buff + f->page_size; info->read_id_bytes = (f->page_size == 2048) ? 4 : 2; /* calculate addressing information */ @@ -788,44 +787,12 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) { uint32_t ndcr = nand_readl(info, NDCR); - struct nand_flash_dev *type = NULL; - uint32_t id = -1, page_per_block, num_blocks; - int i; - page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32; info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; /* set info fields needed to read id */ info->read_id_bytes = (info->page_size == 2048) ? 4 : 2; info->reg_ndcr = ndcr; - pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0); - id = *((uint16_t *)(info->data_buff)); - if (id == 0) - return -ENODEV; - - /* Lookup the flash id */ - for (i = 0; nand_flash_ids[i].name != NULL; i++) { - if (id == nand_flash_ids[i].id) { - type = &nand_flash_ids[i]; - break; - } - } - - if (!type) - return -ENODEV; - - /* fill the missing flash information */ - i = __ffs(page_per_block * info->page_size); - num_blocks = type->chipsize << (20 - i); - - /* calculate addressing information */ - info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1; - - if (num_blocks * page_per_block > 65536) - info->row_addr_cycles = 3; - else - info->row_addr_cycles = 2; - info->ndtr0cs0 = nand_readl(info, NDTR0CS0); info->ndtr1cs0 = nand_readl(info, NDTR1CS0); info->cmdset = &default_cmdset; @@ -937,14 +904,17 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd) struct pxa3xx_nand_info *info = mtd->priv; struct platform_device *pdev = info->pdev; struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; + struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}}; const struct pxa3xx_nand_flash *f = NULL; struct nand_chip *chip = mtd->priv; uint32_t id = -1; + uint64_t chipsize; int i, ret; - if (pdata->keep_config) + if (pdata->keep_config) { if (pxa3xx_nand_detect_config(info) == 0) - return 0; + goto KEEP_CONFIG; + } ret = pxa3xx_nand_sensing(info); if (!ret) { @@ -974,22 +944,11 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd) f = &builtin_flash_types[i - pdata->num_flash + 1]; /* find the chip in default list */ - if (f->chip_id == id) { - pxa3xx_nand_config_flash(info, f); - mtd->writesize = f->page_size; - mtd->writesize_shift = ffs(mtd->writesize) - 1; - mtd->writesize_mask = (1 << mtd->writesize_shift) - 1; - mtd->oobsize = mtd->writesize / 32; - mtd->erasesize = f->page_size * f->page_per_block; - mtd->erasesize_shift = ffs(mtd->erasesize) - 1; - mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1; - - mtd->name = mtd_names[0]; + if (f->chip_id == id) break; - } } - if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) { + if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { kfree(mtd); info->mtd = NULL; printk(KERN_ERR "ERROR!! flash not defined!!!\n"); @@ -997,20 +956,28 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd) return -EINVAL; } + pxa3xx_nand_config_flash(info, f); + pxa3xx_flash_ids[0].name = f->name; + pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff; + pxa3xx_flash_ids[0].pagesize = f->page_size; + chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; + pxa3xx_flash_ids[0].chipsize = chipsize >> 20; + pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; + pxa3xx_flash_ids[0].options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0; +KEEP_CONFIG: + if (nand_scan_ident(mtd, 1, pxa3xx_flash_ids)) + return -ENODEV; + /* calculate addressing information */ + info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1; + info->oob_buff = info->data_buff + mtd->writesize; + if ((mtd->size >> chip->page_shift) > 65536) + info->row_addr_cycles = 3; + else + info->row_addr_cycles = 2; + mtd->name = mtd_names[0]; chip->ecc.mode = NAND_ECC_HW; - chip->ecc.size = f->page_size; - chip->chipsize = (uint64_t)f->num_blocks * f->page_per_block - * f->page_size; - mtd->size = chip->chipsize; - - /* Calculate the address shift from the page size */ - chip->page_shift = ffs(mtd->writesize) - 1; - chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1; - chip->numchips = 1; - chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1; - - chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0; - chip->options |= NAND_NO_AUTOINCR; + chip->ecc.size = mtd->writesize; + chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0; chip->options |= NAND_NO_READRDY; chip->options |= NAND_USE_FLASH_BBT; diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h index 0bf1bcf..6d9212b 100644 --- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h @@ -30,6 +30,7 @@ struct pxa3xx_nand_cmdset { }; struct pxa3xx_nand_flash { + char *name; uint32_t chip_id; uint16_t page_per_block; /* Pages per block (PG_PER_BLK) */ uint16_t page_size; /* Page size in bytes (PAGE_SZ) */ diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 617bc69..d4e34aa 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -214,15 +214,15 @@ static struct pxa3xx_nand_timing __devinitdata timing[] = { #define NAND_SETTING_MICRON &default_cmdset, &timing[2] #define NAND_SETTING_ST &default_cmdset, &timing[3] static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = { - { 0, 0, 2048, 8, 8, 0, NAND_SETTING_DEFAULT, }, - { 0x46ec, 32, 512, 16, 16, 4096, NAND_SETTING_SAMSUNG, }, - { 0xdaec, 64, 2048, 8, 8, 2048, NAND_SETTING_SAMSUNG, }, - { 0xd7ec, 128, 4096, 8, 8, 8192, NAND_SETTING_SAMSUNG, }, - { 0xa12c, 64, 2048, 8, 8, 1024, NAND_SETTING_MICRON, }, - { 0xb12c, 64, 2048, 16, 16, 1024, NAND_SETTING_MICRON, }, - { 0xdc2c, 64, 2048, 8, 8, 4096, NAND_SETTING_MICRON, }, - { 0xcc2c, 64, 2048, 16, 16, 4096, NAND_SETTING_MICRON, }, - { 0xba20, 64, 2048, 16, 16, 2048, NAND_SETTING_ST, }, +{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, NAND_SETTING_DEFAULT, }, +{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, NAND_SETTING_SAMSUNG, }, +{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, NAND_SETTING_SAMSUNG, }, +{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, NAND_SETTING_SAMSUNG, }, +{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, NAND_SETTING_MICRON, }, +{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, NAND_SETTING_MICRON, }, +{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, NAND_SETTING_MICRON, }, +{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, NAND_SETTING_MICRON, }, +{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, NAND_SETTING_ST, }, };