@@ -119,8 +119,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {
static struct pxa3xx_nand_platform_data aspenite_nand_info = {
.enable_arbiter = 1,
- .parts = aspenite_nand_partitions,
- .nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
+ .parts[0] = aspenite_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(aspenite_nand_partitions),
};
static void __init common_init(void)
b/arch/arm/mach-mmp/avengers_lite.c
@@ -32,12 +32,63 @@ static unsigned long
avengers_lite_pin_config_V16F[] __initdata = {
GPIO89_UART2_RXD,
};
+static struct mtd_partition avengers_nand_partitions_0[] = {
+ {
+ .name = "bootloader",
+ .offset = 0,
+ .size = SZ_1M,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = (SZ_2M + SZ_1M),
+ }, {
+ .name = "mass0",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_48M,
+ }
+};
+
+static struct mtd_partition avengers_nand_partitions_1[] = {
+ {
+ .name = "reserved",
+ .offset = 0,
+ .size = SZ_2M,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "filesystem",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_512M,
+ }, {
+ .name = "mass1",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_16M,
+ }, {
+ .name = "mass2",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_256M,
+ }
+};
+
+static struct pxa3xx_nand_platform_data avengers_nand_info;
+static void __init avengers_init_flash(void)
+{
+ avengers_nand_info.parts[0] = avengers_nand_partitions_0;
+ avengers_nand_info.nr_parts[0] = ARRAY_SIZE(avengers_nand_partitions_0);
+ avengers_nand_info.parts[1] = avengers_nand_partitions_1;
+ avengers_nand_info.nr_parts[1] = ARRAY_SIZE(avengers_nand_partitions_1);
+ avengers_nand_info.enable_arbiter = 1;
+ avengers_nand_info.naked_cmd_support = 1;
+ pxa168_add_nand(&avengers_nand_info);
+}
+
static void __init avengers_lite_init(void)
{
mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));
/* on-chip devices */
pxa168_add_uart(2);
+ avengers_init_flash();
}
MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
@@ -416,8 +416,8 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
.enable_arbiter = 1,
.keep_config = 1,
- .parts = cm_x300_nand_partitions,
- .nr_parts = ARRAY_SIZE(cm_x300_nand_partitions),
+ .parts[0] = cm_x300_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(cm_x300_nand_partitions),
};
static void __init cm_x300_init_nand(void)
b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -188,8 +188,8 @@ static struct mtd_partition colibri_nand_partitions[] = {
static struct pxa3xx_nand_platform_data colibri_nand_info = {
.enable_arbiter = 1,
.keep_config = 1,
- .parts = colibri_nand_partitions,
- .nr_parts = ARRAY_SIZE(colibri_nand_partitions),
+ .parts[0] = colibri_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(colibri_nand_partitions),
};
void __init colibri_pxa3xx_init_nand(void)
@@ -326,8 +326,8 @@ static struct mtd_partition littleton_nand_partitions[] = {
static struct pxa3xx_nand_platform_data littleton_nand_info = {
.enable_arbiter = 1,
- .parts = littleton_nand_partitions,
- .nr_parts = ARRAY_SIZE(littleton_nand_partitions),
+ .parts[0] = littleton_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(littleton_nand_partitions),
};
static void __init littleton_init_nand(void)
@@ -389,10 +389,10 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = {
};
static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
- .enable_arbiter = 1,
- .keep_config = 1,
- .parts = mxm_8x10_nand_partitions,
- .nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions)
+ .enable_arbiter = 1,
+ .keep_config = 1,
+ .parts[0] = mxm_8x10_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(mxm_8x10_nand_partitions)
};
static void __init mxm_8x10_nand_init(void)
@@ -350,8 +350,8 @@ static struct mtd_partition raumfeld_nand_partitions[] = {
static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
.enable_arbiter = 1,
.keep_config = 1,
- .parts = raumfeld_nand_partitions,
- .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions),
+ .parts[0] = raumfeld_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(raumfeld_nand_partitions),
};
/**
@@ -356,8 +356,8 @@ static struct mtd_partition zylonite_nand_partitions[] = {
static struct pxa3xx_nand_platform_data zylonite_nand_info = {
.enable_arbiter = 1,
- .parts = zylonite_nand_partitions,
- .nr_parts = ARRAY_SIZE(zylonite_nand_partitions),
+ .parts[0] = zylonite_nand_partitions,
+ .nr_parts[0] = ARRAY_SIZE(zylonite_nand_partitions),
};
static void __init zylonite_init_nand(void)
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -4,6 +4,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#define NUM_CHIP_SELECT (2)
struct pxa3xx_nand_platform_data {
/* the data flash bus is shared between the Static Memory
@@ -15,8 +16,8 @@ struct pxa3xx_nand_platform_data {
/* allow platform code to keep OBM/bootloader defined NFC config */
int keep_config;
- const struct mtd_partition *parts;
- unsigned int nr_parts;
+ const struct mtd_partition *parts[NUM_CHIP_SELECT];
+ unsigned int nr_parts[NUM_CHIP_SELECT];
};
extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info);
@@ -98,6 +98,8 @@
#define nand_readl(info, off) \
__raw_readl((info)->mmio_base + (off))
+#define get_mtd_by_info(info) \
+ (struct mtd_info *)((void *)info - sizeof(struct mtd_info))
/* error code and state */
enum {
@@ -158,60 +160,62 @@ struct pxa3xx_nand_flash {
struct pxa3xx_nand_info {
struct nand_chip nand_chip;
- struct platform_device *pdev;
-
- struct clk *clk;
- void __iomem *mmio_base;
- unsigned long mmio_phys;
-
- unsigned int buf_start;
- unsigned int buf_count;
-
- struct mtd_info *mtd;
- /* DMA information */
- int drcmr_dat;
- int drcmr_cmd;
-
+ uint32_t page_size; /* page size of attached chip */
unsigned char *data_buff;
unsigned char *oob_buff;
+ uint32_t buf_start;
+ uint32_t buf_count;
+
+ /* dma related */
+ int data_dma_ch;
dma_addr_t data_buff_phys;
- size_t data_buff_size;
- int data_dma_ch;
- struct pxa_dma_desc *data_desc;
dma_addr_t data_desc_addr;
+ struct pxa_dma_desc *data_desc;
+ uint8_t chip_select;
+ uint8_t use_ecc; /* use HW ECC ? */
- uint32_t reg_ndcr;
-
- /* saved column/page_addr during CMD_SEQIN */
- int seqin_column;
- int seqin_page_addr;
+ /* calculated from pxa3xx_nand_flash data */
+ uint8_t col_addr_cycles;
+ uint8_t row_addr_cycles;
+ uint8_t read_id_bytes;
- /* relate to the command */
- unsigned int state;
+ /* cached register value */
+ uint32_t reg_ndcr;
+ uint32_t ndtr0cs0;
+ uint32_t ndtr1cs0;
+ uint32_t ndcb0;
+ uint32_t ndcb1;
+ uint32_t ndcb2;
- int use_ecc; /* use HW ECC ? */
- int use_dma; /* use DMA ? */
+ void *nand_data;
+};
- unsigned int page_size; /* page size of attached chip */
- unsigned int data_size; /* data size in FIFO */
- int retcode;
+struct pxa3xx_nand {
+ struct clk *clk;
+ void __iomem *mmio_base;
+ unsigned long mmio_phys;
+ struct nand_hw_control controller;
struct completion cmd_complete;
+ struct platform_device *pdev;
- /* generated NDCBx register values */
- uint32_t ndcb0;
- uint32_t ndcb1;
- uint32_t ndcb2;
+ uint8_t chip_select;
+ uint8_t use_ecc;
+ uint8_t use_dma;
+ uint8_t wait_mode;
- /* timing calcuted from setting */
- uint32_t ndtr0cs0;
- uint32_t ndtr1cs0;
+ /* relate to the command */
+ uint32_t state;
+ uint32_t command;
+ uint16_t data_size; /* data size in FIFO */
+ uint16_t oob_size;
+ uint32_t bad_count;
+ uint32_t retcode;
- /* calculated from pxa3xx_nand_flash data */
- size_t oob_size;
- size_t read_id_bytes;
+ /* DMA information */
+ uint32_t drcmr_dat;
+ uint32_t drcmr_cmd;
- unsigned int col_addr_cycles;
- unsigned int row_addr_cycles;
+ struct pxa3xx_nand_info *info[NUM_CHIP_SELECT];
};
static int use_dma = 1;
@@ -240,6 +244,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
{ 0, 0, 0, 0, 0, 0, { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, },
{ 0x46ec, 32, 512, 16, 16, 4096, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, },
{ 0xdaec, 64, 2048, 8, 8, 2048, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, },
+{ 0xd3ec, 128, 2048, 8, 8, 4096, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, },
{ 0xd7ec, 128, 4096, 8, 8, 8192, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, },
{ 0xa12c, 64, 2048, 8, 8, 1024, { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, },