From patchwork Wed Aug 18 14:36:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 62046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EDFC7B70D1 for ; Thu, 19 Aug 2010 00:38:09 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Oljl9-0004zx-LP; Wed, 18 Aug 2010 14:36:55 +0000 Received: from mail-gy0-f177.google.com ([209.85.160.177]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OljkR-0004ir-4m; Wed, 18 Aug 2010 14:36:12 +0000 Received: by gyf2 with SMTP id 2so254820gyf.36 for ; Wed, 18 Aug 2010 07:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=ePs9Tmz/E4ej2Cs2lueaNtE7jM82WlW8QfnUTDaG8QY=; b=uCHTdK8/J874MIuCGA7MlBfSWDY9BskEWOcHR6Bjzk/Q6eFyh3wv2g8bTvFmh45UrR LAOKjb2eDcEQ/COglrxXIzAszhfpSgefafnBUu00wNHd9nTzMZwKxFpeE6kvy8qRNqA1 9c7ktisYW/Q+B06wwryqb5yQ6cqa+/L5HdyhQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=SfzRqqK0qrxX/TtWeY3TdJh4FmAHX2Rvbp/7yHYm/YPLJB9tQ0ylECz6wI6p/3o7+G OZJ4Ir/4zqmXkW7J5QRtO6v8JcD0xVScEPHtD1X9wsPoheF5u2LA12GKYFnOlaHJWFRC UJNThKMYqfkq2ToPhYsg6lUvYfUcytVYcXnbA= MIME-Version: 1.0 Received: by 10.151.63.30 with SMTP id q30mr514859ybk.154.1282142170401; Wed, 18 Aug 2010 07:36:10 -0700 (PDT) Received: by 10.151.114.1 with HTTP; Wed, 18 Aug 2010 07:36:10 -0700 (PDT) Date: Wed, 18 Aug 2010 22:36:10 +0800 Message-ID: Subject: [PATCH 3/5] pxa3xx_nand: introduce default timing to reduce read id times From: Haojian Zhuang To: Eric Miao , David Woodhouse , linux-arm-kernel , linux-mtd@lists.infradead.org X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100818_103611_419556_F73B8BE5 X-CRM114-Status: GOOD ( 19.73 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (haojian.zhuang[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From 5235f4075c3d2224a2d2351e2800ef42920ebd75 Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Wed, 18 Aug 2010 18:00:03 +0800 Subject: [PATCH 3/5] pxa3xx_nand: introduce default timing to reduce read id times We certainly don't need to send read id command times by times, since we already know what the id is after the first read id... So create a default timing which could ensure it would successfully read id out all supported chip. Then follow the build-in table to reconfigure the timing. Signed-off-by: Lei Wen Signed-off-by: Haojian Zhuang Acked-by: Eric Miao --- drivers/mtd/nand/pxa3xx_nand.c | 68 +++++++++++++++++++-------------------- 1 files changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 0b63f9c..8385e3a 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -190,22 +190,27 @@ static struct pxa3xx_nand_cmdset default_cmdset = { }; static struct pxa3xx_nand_timing timing[] = { - { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, - { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, - { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, + { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, + { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, + { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, + { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, }; static struct pxa3xx_nand_flash builtin_flash_types[] = { - { 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[0] }, - { 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[0] }, - { 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[0] }, - { 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[1] }, - { 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[1] }, - { 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[1] }, - { 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[1] }, - { 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[2] }, + { 0, 0, 2048, 8, 8, 0, &default_cmdset, &timing[0] }, + { 0x46ec, 32, 512, 16, 16, 4096, &default_cmdset, &timing[1] }, + { 0xdaec, 64, 2048, 8, 8, 2048, &default_cmdset, &timing[1] }, + { 0xd7ec, 128, 4096, 8, 8, 8192, &default_cmdset, &timing[1] }, + { 0xa12c, 64, 2048, 8, 8, 1024, &default_cmdset, &timing[2] }, + { 0xb12c, 64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] }, + { 0xdc2c, 64, 2048, 8, 8, 4096, &default_cmdset, &timing[2] }, + { 0xcc2c, 64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] }, + { 0xba20, 64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] }, }; +/* Define a default flash type setting serve as flash detecting only */ +#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) + #define NDTR0_tCH(c) (min((c), 7) << 19) #define NDTR0_tCS(c) (min((c), 7) << 16) #define NDTR0_tWH(c) (min((c), 7) << 11) @@ -945,36 +950,29 @@ static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info, if (pxa3xx_nand_detect_config(info) == 0) return 0; - for (i = 0; inum_flash; ++i) { - f = pdata->flash + i; - - if (pxa3xx_nand_config_flash(info, f)) - continue; - - if (__readid(info, &id)) - continue; - - if (id == f->chip_id) - return 0; - } - - for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) { - - f = &builtin_flash_types[i]; - - if (pxa3xx_nand_config_flash(info, f)) - continue; - - if (__readid(info, &id)) - continue; - - if (id == f->chip_id) + /* we use default timing to detect id */ + f = DEFAULT_FLASH_TYPE; + pxa3xx_nand_config_flash(info, f); + if (__readid(info, &id)) + goto fail_detect; + + for (i=0; inum_flash - 1; i++) { + /* we first choose the flash definition from platfrom */ + if (i < pdata->num_flash) + f = pdata->flash + i; + else + f = &builtin_flash_types[i - pdata->num_flash + 1]; + if (f->chip_id == id) { + dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id); + pxa3xx_nand_config_flash(info, f); return 0; + } } dev_warn(&info->pdev->dev, "failed to detect configured nand flash; found %04x instead of\n", id); +fail_detect: return -ENODEV; }