@@ -29,7 +29,10 @@
#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
#define NAND_STOP_DELAY (2 * HZ/50)
#define PAGE_CHUNK_SIZE (2048)
+#define OOB_CHUNK_SIZE (64)
#define BCH_THRESHOLD (8)
+#define CMD_POOL_SIZE (5)
+#define READ_ID_BYTES (4)
/* registers and bit definitions */
#define NDCR (0x00) /* Control register */
@@ -39,33 +42,50 @@
#define NDPCR (0x18) /* Page Count Register */
#define NDBDR0 (0x1C) /* Bad Block Register 0 */
#define NDBDR1 (0x20) /* Bad Block Register 1 */
+#define NDREDEL (0x24) /* Read Enable Return Delay Register */
#define NDECCCTRL (0x28) /* ECC Control Register */
+#define NDBZCNT (0x2C) /* Timer for NDRnB0 and NDRnB1 */
#define NDDB (0x40) /* Data Buffer */
#define NDCB0 (0x48) /* Command Buffer0 */
#define NDCB1 (0x4C) /* Command Buffer1 */
#define NDCB2 (0x50) /* Command Buffer2 */
#define NDCR_SPARE_EN (0x1 << 31)
-#define NDSR_ERR_CNT_MASK (0x1F << 16)
-#define NDSR_ERR_CNT(x) (((x) << 16) & NDSR_ERR_CNT_MASK)
#define NDCR_ECC_EN (0x1 << 30)
#define NDCR_DMA_EN (0x1 << 29)
#define NDCR_ND_RUN (0x1 << 28)
#define NDCR_DWIDTH_C (0x1 << 27)
#define NDCR_DWIDTH_M (0x1 << 26)
-#define NDCR_PAGE_SZ (0x1 << 24)
-#define NDCR_NCSX (0x1 << 23)
-#define NDCR_ND_MODE (0x3 << 21)
+#define NDCR_PAGE_SZ_MASK (0x3 << 24)
+#define NDCR_PAGE_SZ(x) (((x) << 24) & NDCR_PAGE_SZ_MASK)
+#define NDCR_SEQ_DIS (0x1 << 23)
+#define NDCR_ND_STOP (0x1 << 22)
+#define NDCR_FORCE_CSX (0x1 << 21)
#define NDCR_CLR_PG_CNT (0x1 << 20)
#define NDCR_STOP_ON_UNCOR (0x1 << 19)
#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
#define NDCR_RA_START (0x1 << 15)
-#define NDCR_PG_PER_BLK (0x1 << 14)
+#define NDCR_PG_PER_BLK_MASK (0x3 << 13)
+#define NDCR_PG_PER_BLK(x) (((x) << 13) & NDCR_PG_PER_BLK_MASK)
#define NDCR_ND_ARB_EN (0x1 << 12)
#define NDCR_INT_MASK (0xFFF)
+#define NDCR_RDYM (0x1 << 11)
+#define NDCR_CS0_PAGEDM (0x1 << 10)
+#define NDCR_CS1_PAGEDM (0x1 << 9)
+#define NDCR_CS0_CMDDM (0x1 << 8)
+#define NDCR_CS1_CMDDM (0x1 << 7)
+#define NDCR_CS0_BBDM (0x1 << 6)
+#define NDCR_CS1_BBDM (0x1 << 5)
+#define NDCR_UNCERRM (0x1 << 4)
+#define NDCR_CORERRM (0x1 << 3)
+#define NDCR_WRDREQM (0x1 << 2)
+#define NDCR_RDDREQM (0x1 << 1)
+#define NDCR_WRCMDREQM (0x1)
+#define NDSR_ERR_CNT_MASK (0x1F << 16)
+#define NDSR_ERR_CNT(x) (((x) << 16) & NDSR_ERR_CNT_MASK)
#define NDSR_MASK (0xfff)
#define NDSR_RDY (0x1 << 12)
#define NDSR_FLASH_RDY (0x1 << 11)
@@ -81,6 +101,8 @@
#define NDSR_RDDREQ (0x1 << 1)
#define NDSR_WRCMDREQ (0x1)
+#define NDCB0_CMD_XTYPE_MASK (0x7 << 29)
+#define NDCB0_CMD_XTYPE(x) (((x) << 29) & NDCB0_CMD_XTYPE_MASK)
#define NDCB0_ST_ROW_EN (0x1 << 26)
#define NDCB0_AUTO_RS (0x1 << 25)
#define NDCB0_CSEL (0x1 << 24)
@@ -110,6 +132,7 @@
#define get_mtd_by_info(info) \
(struct mtd_info *)((void *)info - sizeof(struct mtd_info))
+#define STATE_MASK (0x3f)
/* error code and state */
enum {
ERR_NONE = 0,
@@ -142,7 +165,6 @@ struct pxa3xx_nand_info {
/* calculated from pxa3xx_nand_flash data */
uint8_t col_addr_cycles;
uint8_t row_addr_cycles;
- uint8_t read_id_bytes;
/* cached register value */
uint32_t reg_ndcr;
@@ -178,7 +200,8 @@ struct pxa3xx_nand {
unsigned char *oob_buff;
uint32_t buf_start;
uint32_t buf_count;
- uint8_t total_cmds;
+ uint16_t data_column;
+ uint16_t oob_column;
/* relate to the command */
uint8_t chip_select;
@@ -187,8 +210,11 @@ struct pxa3xx_nand {
int use_dma; /* use DMA ? */
int retcode;
- /* generated NDCBx register values */
- uint32_t ndcb0;
+ /* cached register value */
+ uint8_t cmd_seqs;
+ uint8_t total_cmds;
+ uint8_t wait_ready[CMD_POOL_SIZE];
+ uint32_t ndcb0[CMD_POOL_SIZE];
uint32_t ndcb1;
uint32_t ndcb2;
};
@@ -235,6 +261,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, ECC_HAMMIN, 1024,
NAND_SETTING_MICRON, },
{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },