b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -11,6 +11,7 @@ enum {
};
struct pxa3xx_nand_timing {
+ unsigned int tADL; /* Adress to Write Data delay */
unsigned int tCH; /* Enable signal hold time */
unsigned int tCS; /* Enable signal setup time */
unsigned int tWH; /* ND_nWE high duration */
@@ -18,6 +19,7 @@ struct pxa3xx_nand_timing {
unsigned int tRH; /* ND_nRE high duration */
unsigned int tRP; /* ND_nRE pulse width */
unsigned int tR; /* ND_nWE high to ND_nRE low for read */
+ unsigned int tRHW; /* delay for next command issue */
unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */
unsigned int tAR; /* ND_ALE low to ND_nRE low delay */
};
@@ -246,10 +246,10 @@ static struct pxa3xx_nand_cmdset default_cmdset = {
};
static struct pxa3xx_nand_timing __devinitdata timing[] = {
- { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
- { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
- { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
- { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
+ { 0, 40, 80, 60, 100, 80, 100, 90000, 0, 400, 40, },
+ { 200, 10, 0, 20, 40, 30, 40, 11123, 20, 110, 10, },
+ { 0, 10, 25, 15, 25, 15, 30, 25000, 0, 60, 10, },
+ { 0, 10, 35, 15, 25, 15, 25, 25000, 0, 60, 10, },
};
#define NAND_SETTING_DEFAULT &default_cmdset, &timing[0]
@@ -272,16 +272,20 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
-#define NDTR0_tCH(c) (min((c), 7) << 19)
-#define NDTR0_tCS(c) (min((c), 7) << 16)
-#define NDTR0_tWH(c) (min((c), 7) << 11)
-#define NDTR0_tWP(c) (min((c), 7) << 8)
-#define NDTR0_tRH(c) (min((c), 7) << 3)
-#define NDTR0_tRP(c) (min((c), 7) << 0)
-
-#define NDTR1_tR(c) (min((c), 65535) << 16)
-#define NDTR1_tWHR(c) (min((c), 15) << 4)
-#define NDTR1_tAR(c) (min((c), 15) << 0)
+#define NDTR0_tADL(c) (min_t(uint32_t, (c), 31) << 27)
+#define NDTR0_tCH(c) (min_t(uint32_t, (c), 7) << 19)
+#define NDTR0_tCS(c) (min_t(uint32_t, (c), 7) << 16)
+#define NDTR0_tWH(c) (min_t(uint32_t, (c), 7) << 11)
+#define NDTR0_tWP(c) (min_t(uint32_t, (c), 7) << 8)
+#define NDTR0_ETRP (0x1 << 6)
+#define NDTR0_tRH(c) (min_t(uint32_t, (c), 7) << 3)
+#define NDTR0_tRP(c) (min_t(uint32_t, (c), 7) << 0)
+
+#define NDTR1_tR(c) (min_t(uint32_t, (c), 65535) << 16)
+#define NDTR1_PRESCALE (0x1 << 14)
+#define NDTR1_tRHW(c) (min_t(uint32_t, (c), 3) << 8)
+#define NDTR1_tWHR(c) (min_t(uint32_t, (c), 15) << 4)
+#define NDTR1_tAR(c) (min_t(uint32_t, (c), 15) << 0)
/* convert nano-seconds to nand flash controller clock cycles */