From patchwork Tue Nov 4 13:25:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bpqw X-Patchwork-Id: 406608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5FADD14009E for ; Wed, 5 Nov 2014 00:28:27 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xle8i-0004yf-QL; Tue, 04 Nov 2014 13:27:16 +0000 Received: from mailout.micron.com ([137.201.242.129]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xle8g-0004gA-EE; Tue, 04 Nov 2014 13:27:15 +0000 Received: from mail.micron.com (bowex36-b.micron.com [137.201.85.142]) by mailout.micron.com (8.14.4/8.14.6) with ESMTP id sA4DQXTr031998 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=FAIL); Tue, 4 Nov 2014 06:26:34 -0700 Received: from BOWEX36-D.micron.com (137.201.85.144) by BOWEX36-B.micron.com (137.201.85.142) with Microsoft SMTP Server (TLS) id 15.0.995.29; Tue, 4 Nov 2014 06:26:33 -0700 Received: from BOWEX36-D.micron.com (137.201.85.144) by BOWEX36-D.micron.com (137.201.85.144) with Microsoft SMTP Server (TLS) id 15.0.995.29; Tue, 4 Nov 2014 06:26:32 -0700 Received: from NTXXIACAS02.xacn.micron.com (10.167.69.56) by BOWEX36-D.micron.com (137.201.85.144) with Microsoft SMTP Server (TLS) id 15.0.995.29 via Frontend Transport; Tue, 4 Nov 2014 06:26:32 -0700 Received: from NTXXIAMBX02.xacn.micron.com ([fe80::e19a:c3ed:119d:6971]) by NTXXIACAS02.xacn.micron.com ([::1]) with mapi id 14.03.0210.002; Tue, 4 Nov 2014 21:25:14 +0800 From: bpqw To: Marek Vasut , "dwmw2@infradead.org" , Brian Norris Subject: [PATCH 1/1 v4] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor Thread-Topic: [PATCH 1/1 v4] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor Thread-Index: AQHP2KkjagwG2in0R7+6ioZ2PHnYSpwTG1RugAKuPPCAAgpzkIADfZeAgBhBsxCABMQ/MIAGOkDwgASw+FCADXBPcA== Date: Tue, 4 Nov 2014 13:25:14 +0000 Message-ID: References: <201409251211.57183.marex@denx.de> <201409261046.07132.marex@denx.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.167.84.5] x-tm-as-product-ver: SMEX-10.0.0.4152-7.000.1014-21074.005 x-tm-as-result: No--32.293000-0.000000-31 x-tm-as-user-approved-sender: Yes x-tm-as-user-blocked-sender: No x-mt-checkinternalsenderrule: True MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.73 on 137.201.131.43 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141104_052714_547337_798A2F43 X-CRM114-Status: GOOD ( 10.77 ) X-Spam-Score: -2.9 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [137.201.242.129 listed in list.dnswl.org] -0.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record Cc: "grmoore@altera.com" , "linux-mtd@lists.infradead.org" , "shijie8@gmail.com" , "linux-kernel@vger.kernel.org" , "geert+renesas@glider.be" X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in quad I/O mode. Signed-off-by: bean huo Acked-by: Marek Vasut --- v1-v2:modified to that capture wait_till_ready() return value,if error,directly return its the value. v2-v3:directly use the reurning error value of read_reg and write_reg,instead of -EINVAL. V3-v4: Modify commit logs that wraped into 80 columns drivers/mtd/spi-nor/spi-nor.c | 46 +++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 6 ++++++ 2 files changed, 52 insertions(+) -- 1.7.9.5 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b5ad6be..486b167 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -878,6 +878,45 @@ static int spansion_quad_enable(struct spi_nor *nor) return 0; } +static int micron_quad_enable(struct spi_nor *nor) { + int ret, val; + + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); + if (ret < 0) { + dev_err(nor->dev, "error %d reading EVCR\n", ret); + return ret; + } + + write_enable(nor); + + /* set EVCR ,enable quad I/O */ + nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON; + ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0); + if (ret < 0) { + dev_err(nor->dev, + "error while writing EVCR register\n"); + return ret; + } + + ret = wait_till_ready(nor); + if (ret) + return ret; + + /* read EVCR and check it */ + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); + if (ret < 0) { + dev_err(nor->dev, "error %d reading EVCR\n", ret); + return ret; + } + if (val & EVCR_QUAD_EN_MICRON) { + dev_err(nor->dev, "Micron EVCR Quad bit not clear\n"); + return -EINVAL; + } + + return 0; +} + static int set_quad_mode(struct spi_nor *nor, u32 jedec_id) { int status; @@ -890,6 +929,13 @@ static int set_quad_mode(struct spi_nor *nor, u32 jedec_id) return -EINVAL; } return status; + case CFI_MFR_ST: + status = micron_quad_enable(nor); + if (status) { + dev_err(nor->dev, "Micron quad-read not enabled\n"); + return -EINVAL; + } + return status; default: status = spansion_quad_enable(nor); if (status) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 9e6294f..d71b659 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -56,6 +56,10 @@ /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ +/* Used for Micron flashes only. */ +#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ +#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */ + /* Status Register bits. */ #define SR_WIP 1 /* Write in progress */ #define SR_WEL 2 /* Write enable latch */ @@ -67,6 +71,8 @@ #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ +#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */ + /* Flag Status Register bits */ #define FSR_READY 0x80