| Message ID | 20260827-mtd_eraze_to_fix-v2-1-1395ae4fb795@intel.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] mtd: mtd_intel_dg: reset poll counter for each erase | expand |
On Thu, 27 Aug 2026 08:11:56 +0300, Alexander Usyskin wrote: > The non-posted erase polling counter is initialized only once per MTD > erase request. Large requests therefore share the polling budget across > all 4K erase commands and can fail with -ETIME even though no individual > command timed out. > > Reset the counter for each 4K erase command so every operation gets the > intended completion timeout. > > [...] Applied to mtd/fixes, thanks! [1/1] mtd: mtd_intel_dg: reset poll counter for each erase commit: e0a84c2fc29dc23f9331a4a9f236ef61c941c3a4 Patche(s) should be available on mtd/linux.git and will be part of the next PR (provided that no robot complains by then). Kind regards, Miquèl
diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_intel_dg.c index f2fa8f68d190..6e226c0c7f17 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -387,7 +387,7 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_a void __iomem *base2 = nvm->base2; void __iomem *base = nvm->base; const u32 block = 0x10; - u32 iter = 0; + u32 iter; u32 reg; u64 i; @@ -396,6 +396,7 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_a iowrite32(region << 24 | block, base + NVM_ERASE_REG); if (nvm->non_posted_erase) { /* Wait for Erase Done */ + iter = 0; reg = ioread32(base2 + NVM_DEBUG_REG); while (!(reg & NVM_NON_POSTED_ERASE_DONE) && ++iter < NVM_NON_POSTED_ERASE_DONE_ITER) {