| Message ID | 20260825171737.776052-15-s-k6@ti.com |
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Subject: [PATCH v9 14/18] spi: cadence-quadspi: reprogram PHY DLL on runtime
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Date: Tue, 25 Aug 2026 22:47:33 +0530
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Content preview: The PHY DLL loses its programmed delay values and lock when
the OSPI controller is power-gated during runtime suspend. On resume,
cqspi_controller_init()
reinitialises the controller but does not touc [...]
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spi: cadence-quadspi: add PHY tuning support
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diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 530335f002fb..94d67e8bcfbc 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -4029,7 +4029,7 @@ static int cqspi_runtime_suspend(struct device *dev) static int cqspi_runtime_resume(struct device *dev) { struct cqspi_st *cqspi = dev_get_drvdata(dev); - int ret; + int cs, ret; ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); if (ret) @@ -4042,6 +4042,28 @@ static int cqspi_runtime_resume(struct device *dev) cqspi->current_cs = -1; cqspi->sclk = 0; + + for (cs = 0; cs < CQSPI_MAX_CHIPSELECT; cs++) { + struct cqspi_flash_pdata *f_pdata = &cqspi->f_pdata[cs]; + + if (!f_pdata->use_tuned_phy) + continue; + + cqspi_phy_set_dll_master(cqspi); + + cqspi_set_dll(cqspi->iobase, f_pdata->phy_setting.rx, + f_pdata->phy_setting.tx); + ret = cqspi_resync_dll(cqspi); + if (ret) { + dev_warn(dev, "cs%d: PHY DLL resync failed on resume: %d, disabling PHY\n", + cs, ret); + f_pdata->dll_locked = false; + f_pdata->use_tuned_phy = false; + } else { + f_pdata->dll_locked = true; + } + } + return 0; }
The PHY DLL loses its programmed delay values and lock when the OSPI controller is power-gated during runtime suspend. On resume, cqspi_controller_init() reinitialises the controller but does not touch the PHY DLL registers, leaving the DLL in an unlocked state. Any subsequent PHY read or write would then fail at the cqspi_resync_dll() call inside cqspi_tune_phy(). After the controller re-initialisation, iterate over all chip selects and reprogram the DLL with each CS's stored calibrated RX/TX tap counts, then resync to relock it. One invocation per calibrated CS allows each calibration to be independently validated after resume. DLL resync failure is non-fatal: a warning is emitted and resume continues, so the system degrades to non-PHY speed rather than blocking the resume path. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> --- drivers/spi/spi-cadence-quadspi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-)