| Message ID | 20260821114822.4040338-3-s-k6@ti.com |
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From: Santhosh Kumar K <s-k6@ti.com>
To: <broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
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CC: <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
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Krzysztof Kozlowski
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Subject: [PATCH v8 02/18] spi: dt-bindings: add spi-phy-pattern-partition
property
Date: Fri, 21 Aug 2026 17:18:06 +0530
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Content preview: Add spi-phy-pattern-partition,
a per-device phandle property
on the flash sub-node that allows the DT author to directly reference the
partition holding the SPI PHY tuning pattern. Used to locate the [...]
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spi: cadence-quadspi: add PHY tuning support
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diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 891f578b5ac4..277dedcd4246 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -209,5 +209,22 @@ examples: cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; + spi-phy-pattern-partition = <&phy_pattern>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "data"; + reg = <0x0 0x3fc0000>; + }; + + phy_pattern: partition@3fc0000 { + label = "phy-pattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 84976fd3ee1b..cc01b643fe9b 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -123,6 +123,13 @@ properties: description: Delay, in microseconds, after a write transfer. + spi-phy-pattern-partition: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the flash partition holding the pre-programmed SPI PHY tuning + pattern. Used when the device cannot load the pattern dynamically during + PHY tuning. + stacked-memories: description: Several SPI memories can be wired in stacked mode. This basically means that either a device features several chip