@@ -54,6 +54,7 @@
/* FMC2 Controller Registers */
#define FMC2_BCR1 0x0
+#define FMC2_CFGR 0x20
#define FMC2_PCR 0x80
#define FMC2_SR 0x84
#define FMC2_PMEM 0x88
@@ -83,10 +84,14 @@
#define FMC2_BCHDSR2 0x284
#define FMC2_BCHDSR3 0x288
#define FMC2_BCHDSR4 0x28c
+#define FMC2_VERR 0x3f4
/* Register: FMC2_BCR1 */
#define FMC2_BCR1_FMC2EN BIT(31)
+/* Register: FMC2_CFGR */
+#define FMC2_CFGR_FMC2EN BIT(31)
+
/* Register: FMC2_PCR */
#define FMC2_PCR_PWAITEN BIT(1)
#define FMC2_PCR_PBKEN BIT(2)
@@ -208,6 +213,10 @@
#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
+/* Register: FMC2_VERR */
+#define FMC2_VERR_MAJREV GENMASK(7, 4)
+#define FMC2_VERR_MAJREV_2 2
+
enum stm32_fmc2_ecc {
FMC2_ECC_HAM = 1,
FMC2_ECC_BCH4 = 4,
@@ -1397,9 +1406,20 @@ static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
/* Enable FMC2 controller */
- if (nfc->dev == nfc->cdev)
- regmap_update_bits(nfc->regmap, FMC2_BCR1,
- FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
+ if (nfc->dev == nfc->cdev) {
+ u32 verr;
+ u8 majrev;
+
+ regmap_read(nfc->regmap, FMC2_VERR, &verr);
+ majrev = FIELD_GET(FMC2_VERR_MAJREV, verr);
+
+ if (majrev < FMC2_VERR_MAJREV_2)
+ regmap_update_bits(nfc->regmap, FMC2_BCR1,
+ FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
+ else
+ regmap_update_bits(nfc->regmap, FMC2_CFGR,
+ FMC2_CFGR_FMC2EN, FMC2_CFGR_FMC2EN);
+ }
regmap_write(nfc->regmap, FMC2_PCR, pcr);
regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
Add the support of the revision 2 of FMC2 IP. For the NAND controller, the bit used to enable the IP has moved. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-)