| Message ID | 20231108171149.258656-2-biju.das.jz@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add set_iofv() callback | expand |
Hi Biju, On Wed, Nov 8, 2023 at 6:12 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > As per section 8.14 on the AT25QL128A hardware manual, > IO0..IO3 must be set to Hi-Z state for this flash for fast read quad IO. > Snippet from HW manual section 8.14: > The upper nibble of the Mode(M7-4) controls the length of the next FAST > Read Quad IO instruction through the inclusion or exclusion of the first > byte instruction code. The lower nibble bits of the Mode(M3-0) are don't > care. However, the IO pins must be high-impedance before the falling edge > of the first data out clock. > > Add set_iofv() callback for configuring IO fixed values to control the > pin state. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- a/drivers/spi/spi-mem.c > +++ b/drivers/spi/spi-mem.c > @@ -297,6 +297,26 @@ static void spi_mem_access_end(struct spi_mem *mem) > pm_runtime_put(ctlr->dev.parent); > } > > +/** > + * spi_mem_set_iofv() - Set IO fixed values to control the pin state > + * @mem: the SPI memory > + * @val: the IO fixed values Please document the meaning of this value (i.e. what does a set or cleared bit mean?). > + * > + * Set IO fixed values to control the pin state. > + * > + * Return: 0 in case of success, a negative error code otherwise. > + */ > +int spi_mem_set_iofv(struct spi_mem *mem, u32 val) > +{ > + struct spi_controller *ctlr = mem->spi->controller; > + > + if (ctlr->mem_ops && ctlr->mem_ops->set_iofv) > + return ctlr->mem_ops->set_iofv(mem, val); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(spi_mem_set_iofv); > + > /** > * spi_mem_exec_op() - Execute a memory operation > * @mem: the SPI memory Gr{oetje,eeting}s, Geert
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH RFC 1/4] spi: spi-mem: Add set_iofv() callback > > Hi Biju, > > On Wed, Nov 8, 2023 at 6:12 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > As per section 8.14 on the AT25QL128A hardware manual, > > IO0..IO3 must be set to Hi-Z state for this flash for fast read quad IO. > > Snippet from HW manual section 8.14: > > The upper nibble of the Mode(M7-4) controls the length of the next > > FAST Read Quad IO instruction through the inclusion or exclusion of > > the first byte instruction code. The lower nibble bits of the > > Mode(M3-0) are don't care. However, the IO pins must be high-impedance > > before the falling edge of the first data out clock. > > > > Add set_iofv() callback for configuring IO fixed values to control the > > pin state. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/spi/spi-mem.c > > +++ b/drivers/spi/spi-mem.c > > @@ -297,6 +297,26 @@ static void spi_mem_access_end(struct spi_mem *mem) > > pm_runtime_put(ctlr->dev.parent); } > > > > +/** > > + * spi_mem_set_iofv() - Set IO fixed values to control the pin state > > + * @mem: the SPI memory > > + * @val: the IO fixed values > > Please document the meaning of this value (i.e. what does a set or cleared > bit mean?). I will document the value as below, 2 bits for setting IO fixed value for a pin and their values are 00: The output value is 0. 01: The output value is 1. 10: The output value is that of the last bit in the previous transfer (the pin is placed in the Hi-Z state if that was the case in the previous transfer). 11: The pin is placed in the Hi-Z state. Cheers, Biju > > > + * > > + * Set IO fixed values to control the pin state. > > + * > > + * Return: 0 in case of success, a negative error code otherwise. > > + */ > > +int spi_mem_set_iofv(struct spi_mem *mem, u32 val) { > > + struct spi_controller *ctlr = mem->spi->controller; > > + > > + if (ctlr->mem_ops && ctlr->mem_ops->set_iofv) > > + return ctlr->mem_ops->set_iofv(mem, val); > > + > > + return 0; > > +} > > +EXPORT_SYMBOL_GPL(spi_mem_set_iofv); > > + > > /** > > * spi_mem_exec_op() - Execute a memory operation > > * @mem: the SPI memory > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index edd7430d4c05..0cfca8c438e3 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -297,6 +297,26 @@ static void spi_mem_access_end(struct spi_mem *mem) pm_runtime_put(ctlr->dev.parent); } +/** + * spi_mem_set_iofv() - Set IO fixed values to control the pin state + * @mem: the SPI memory + * @val: the IO fixed values + * + * Set IO fixed values to control the pin state. + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int spi_mem_set_iofv(struct spi_mem *mem, u32 val) +{ + struct spi_controller *ctlr = mem->spi->controller; + + if (ctlr->mem_ops && ctlr->mem_ops->set_iofv) + return ctlr->mem_ops->set_iofv(mem, val); + + return 0; +} +EXPORT_SYMBOL_GPL(spi_mem_set_iofv); + /** * spi_mem_exec_op() - Execute a memory operation * @mem: the SPI memory diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 6b0a7dc48a4b..e50f89bf5ba9 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -232,6 +232,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) * limitations (can be alignment or max RX/TX size * limitations) * @supports_op: check if an operation is supported by the controller + * @set_iofv: set IO fixed values to control the pin state * @exec_op: execute a SPI memory operation * @get_name: get a custom name for the SPI mem device from the controller. * This might be needed if the controller driver has been ported @@ -274,6 +275,7 @@ struct spi_controller_mem_ops { int (*adjust_op_size)(struct spi_mem *mem, struct spi_mem_op *op); bool (*supports_op)(struct spi_mem *mem, const struct spi_mem_op *op); + int (*set_iofv)(struct spi_mem *mem, u32 val); int (*exec_op)(struct spi_mem *mem, const struct spi_mem_op *op); const char *(*get_name)(struct spi_mem *mem); @@ -367,6 +369,8 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); bool spi_mem_supports_op(struct spi_mem *mem, const struct spi_mem_op *op); +int spi_mem_set_iofv(struct spi_mem *mem, u32 val); + int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op);
As per section 8.14 on the AT25QL128A hardware manual, IO0..IO3 must be set to Hi-Z state for this flash for fast read quad IO. Snippet from HW manual section 8.14: The upper nibble of the Mode(M7-4) controls the length of the next FAST Read Quad IO instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode(M3-0) are don't care. However, the IO pins must be high-impedance before the falling edge of the first data out clock. Add set_iofv() callback for configuring IO fixed values to control the pin state. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/spi/spi-mem.c | 20 ++++++++++++++++++++ include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 24 insertions(+)