diff mbox series

[v6,3/5] arm: dts: mediatek: Fix existing NAND controller node name

Message ID 20230201021500.26769-4-xiangsheng.hou@mediatek.com
State Changes Requested
Headers show
Series Add MediaTek MT7986 NAND ECC engine support | expand

Commit Message

Xiangsheng Hou Feb. 1, 2023, 2:14 a.m. UTC 
Change the existing node name in order to match NAND controller DT
bindings.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Matthias Brugger Feb. 2, 2023, 12:13 p.m. UTC | #1 
On 01/02/2023 03:14, Xiangsheng Hou wrote:
> Change the existing node name in order to match NAND controller DT
> bindings.
> 
> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Queued for the next merge window, thanks!

> ---
>   arch/arm/boot/dts/mt2701.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 0a0fe8c5a405..ce6a4015fed5 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -359,7 +359,7 @@ thermal: thermal@1100b000 {
>   		mediatek,apmixedsys = <&apmixedsys>;
>   	};
>   
> -	nandc: nfi@1100d000 {
> +	nandc: nand-controller@1100d000 {
>   		compatible = "mediatek,mt2701-nfc";
>   		reg = <0 0x1100d000 0 0x1000>;
>   		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 0a0fe8c5a405..ce6a4015fed5 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -359,7 +359,7 @@  thermal: thermal@1100b000 {
 		mediatek,apmixedsys = <&apmixedsys>;
 	};
 
-	nandc: nfi@1100d000 {
+	nandc: nand-controller@1100d000 {
 		compatible = "mediatek,mt2701-nfc";
 		reg = <0 0x1100d000 0 0x1000>;
 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;