| Message ID | 20230110164703.83413-2-tudor.ambarus@linaro.org |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [1/2] mtd: spi-nor: spansion: Consider reserved bits in CFR5 register | expand |
On 10/01/23 22:17, Tudor Ambarus wrote: > Cypress defines two flavors of configuration registers, volatile and > non volatile, and both use the same bit fields. Rename the bitfields in > the configuration registers so that they can be used for both flavors. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- Reviewed-by: Dhruva Gole <d-gole@ti.com> > drivers/mtd/spi-nor/spansion.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c > index 07fe0f6fdfe3..12a256c0ef4c 100644 > --- a/drivers/mtd/spi-nor/spansion.c > +++ b/drivers/mtd/spi-nor/spansion.c > @@ -15,19 +15,19 @@ > #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ > #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ > #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 > -#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */ > +#define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ > #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 > -#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb > +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb > #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 > -#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ > +#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ > #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 > #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) > #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) > #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) > -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ > +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ > (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ > SPINOR_REG_CYPRESS_CFR5_OPI) > -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 > +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 > #define SPINOR_OP_CYPRESS_RD_FAST 0xee > > /* Cypress SPI NOR flash operations. */ > @@ -57,7 +57,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) > u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; > > /* Use 24 dummy cycles for memory array reads. */ > - *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; > + *buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, > SPINOR_REG_CYPRESS_CFR2V, 1, buf); > @@ -69,7 +69,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) > nor->read_dummy = 24; > > /* Set the octal and DTR enable bits. */ > - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; > + buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, > SPINOR_REG_CYPRESS_CFR5V, 1, buf); > @@ -103,7 +103,7 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) > * in 8D-8D-8D mode. Since there is no register at the next location, > * just initialize the value to 0 and let the transaction go on. > */ > - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; > + buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; > buf[1] = 0; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, > @@ -155,11 +155,11 @@ static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN) > + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) > return 0; > > /* Update the Quad Enable bit. */ > - nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN; > + nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, > SPINOR_REG_CYPRESS_CFR1V, 1, > @@ -210,7 +210,7 @@ static int cypress_nor_set_page_size(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) > + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) > nor->params->page_size = 512; > else > nor->params->page_size = 256;
On 1/11/2023 1:47 AM, Tudor Ambarus wrote: > Cypress defines two flavors of configuration registers, volatile and > non volatile, and both use the same bit fields. Rename the bitfields in > the configuration registers so that they can be used for both flavors. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > --- > drivers/mtd/spi-nor/spansion.c | 22 +++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c > index 07fe0f6fdfe3..12a256c0ef4c 100644 > --- a/drivers/mtd/spi-nor/spansion.c > +++ b/drivers/mtd/spi-nor/spansion.c > @@ -15,19 +15,19 @@ > #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ > #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ > #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 > -#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */ > +#define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ > #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 > -#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb > +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb > #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 > -#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ > +#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ > #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 > #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) > #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) > #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) > -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ > +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ > (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ > SPINOR_REG_CYPRESS_CFR5_OPI) > -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 > +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 > #define SPINOR_OP_CYPRESS_RD_FAST 0xee > > /* Cypress SPI NOR flash operations. */ > @@ -57,7 +57,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) > u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; > > /* Use 24 dummy cycles for memory array reads. */ > - *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; > + *buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, > SPINOR_REG_CYPRESS_CFR2V, 1, buf); > @@ -69,7 +69,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) > nor->read_dummy = 24; > > /* Set the octal and DTR enable bits. */ > - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; > + buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, > SPINOR_REG_CYPRESS_CFR5V, 1, buf); > @@ -103,7 +103,7 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) > * in 8D-8D-8D mode. Since there is no register at the next location, > * just initialize the value to 0 and let the transaction go on. > */ > - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; > + buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; > buf[1] = 0; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, > @@ -155,11 +155,11 @@ static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN) > + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) > return 0; > > /* Update the Quad Enable bit. */ > - nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN; > + nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; > op = (struct spi_mem_op) > CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, > SPINOR_REG_CYPRESS_CFR1V, 1, > @@ -210,7 +210,7 @@ static int cypress_nor_set_page_size(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) > + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) > nor->params->page_size = 512; > else > nor->params->page_size = 256; Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
On Tue, Jan 10 2023, Tudor Ambarus wrote: > Cypress defines two flavors of configuration registers, volatile and > non volatile, and both use the same bit fields. Rename the bitfields in > the configuration registers so that they can be used for both flavors. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Pratyush Yadav <ptyadav@amazon.de>
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 07fe0f6fdfe3..12a256c0ef4c 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -15,19 +15,19 @@ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 -#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */ +#define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 -#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 -#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ +#define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN \ +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ SPINOR_REG_CYPRESS_CFR5_OPI) -#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 +#define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 #define SPINOR_OP_CYPRESS_RD_FAST 0xee /* Cypress SPI NOR flash operations. */ @@ -57,7 +57,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; /* Use 24 dummy cycles for memory array reads. */ - *buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; + *buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR2V, 1, buf); @@ -69,7 +69,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) nor->read_dummy = 24; /* Set the octal and DTR enable bits. */ - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; + buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR5V, 1, buf); @@ -103,7 +103,7 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) * in 8D-8D-8D mode. Since there is no register at the next location, * just initialize the value to 0 and let the transaction go on. */ - buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; + buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; buf[1] = 0; op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, @@ -155,11 +155,11 @@ static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) if (ret) return ret; - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN) + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) return 0; /* Update the Quad Enable bit. */ - nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN; + nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR1V, 1, @@ -210,7 +210,7 @@ static int cypress_nor_set_page_size(struct spi_nor *nor) if (ret) return ret; - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) nor->params->page_size = 512; else nor->params->page_size = 256;
Cypress defines two flavors of configuration registers, volatile and non volatile, and both use the same bit fields. Rename the bitfields in the configuration registers so that they can be used for both flavors. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/mtd/spi-nor/spansion.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)