| Message ID | 20221109231325.7714-1-hamish.martin@alliedtelesis.co.nz |
|---|---|
| State | Accepted |
| Headers | show |
| Series | mtd: rawnand: marvell: Enable NFC/DEVBUS arbiter | expand |
On Wed, 2022-11-09 at 23:13:25 UTC, Hamish Martin wrote: > The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and > a generic local bus controller (Device Bus Controller) that share common > pins. > With a board design that incorporates both a NAND flash and uses > the Device Bus (in our case for an SRAM) accessing the Device Bus device > fails unless the NfArbiterEn bit is set. Setting the bit enables > arbitration between the Device Bus and the NAND flash. > Since there is no obvious downside in enabling this for designs that > don't require arbitration, we always enable it. > > Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks. Miquel
diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index b9d1e96e3334..42c64dcea767 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -114,6 +114,7 @@ #define GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST BIT(20) #define GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST BIT(21) #define GENCONF_SOC_DEVICE_MUX_NFC_INT_EN BIT(25) +#define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27) #define GENCONF_CLK_GATING_CTRL 0x220 #define GENCONF_CLK_GATING_CTRL_ND_GATE BIT(2) #define GENCONF_ND_CLK_CTRL 0x700 @@ -2880,7 +2881,8 @@ static int marvell_nfc_init(struct marvell_nfc *nfc) GENCONF_SOC_DEVICE_MUX_NFC_EN | GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST | GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST | - GENCONF_SOC_DEVICE_MUX_NFC_INT_EN); + GENCONF_SOC_DEVICE_MUX_NFC_INT_EN | + GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN); regmap_update_bits(sysctrl_base, GENCONF_CLK_GATING_CTRL, GENCONF_CLK_GATING_CTRL_ND_GATE,
The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and a generic local bus controller (Device Bus Controller) that share common pins. With a board design that incorporates both a NAND flash and uses the Device Bus (in our case for an SRAM) accessing the Device Bus device fails unless the NfArbiterEn bit is set. Setting the bit enables arbitration between the Device Bus and the NAND flash. Since there is no obvious downside in enabling this for designs that don't require arbitration, we always enable it. Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> --- drivers/mtd/nand/raw/marvell_nand.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)