| Message ID | 20221018091631.11264-1-vkorenblit@sequans.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v4] mtd: rawnand: cadence: support 64-bit slave dma interface | expand |
Hi Valentin, vkorenblit@sequans.com wrote on Tue, 18 Oct 2022 11:16:31 +0200: > 32-bit accesses on 64-bit sdma trigger sdma_err in intr_status register. > > Check dma capabilities before reading/writing from/to sdma interface. > > Link: https://secure-web.cisco.com/1Zuwps3Jm-Qybygq3UAIg4d4S5heggZX1ow8KENGLYXasfYvc72QPuxCC1kbg9_YPoqVYqfCQVlokpkras6hyjajt6RxKCmlzNhUsTu6vdTgufT8upiLvVnbScXuhDTKV539Fk3pwIluw0CMUbizt16dze_fAdyNKJxwNbEzZIq8DIpD8kK9qUCTdhHSEXza7Ytk_EmwCBawUQFBNNV2CzKBaw-vx5t7gbuvlT1IL9WV4bA3nzUs4NLiN1TV2lBuyA28Duk2i-aouwPb5o3UwDHhHxyCQuGos0F-sSxMREQr2Uj4lgR8lfIpFbk6O8o7J3K2i8rXA4TqUYcRD4BxWWNk3nBHVJxW2oVqX6sjS3Vh32VxOnsoXhttu_3UFm3qziOiukq8jXcvoFPvD6kwJutnujcsJzeGzEBSBfUxSHdgZYFyBbHwqqBC298e3uUV-/https%3A%2F%2Flists.01.org%2Fhyperkitty%2Flist%2Fkbuild-all%40lists.01.org%2Fthread%2F3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B%2F What happened to the link? I guess there is some security software interaction here? Should we take the one from your v3? > > Signed-off-by: Valentin Korenblit <vkorenblit@sequans.com> > Reviewed-by: Arnd Bergmann <arnd@arndb.de> > > --- > > Changes v1 -> v2: > - Replaced ioread64_rep by cadence_nand_readsq (suggested by Arnd) > - Replaced iowrite64_rep by cadence_nand_writesq (suggested by Arnd) > - Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not defined > > Changes v2 -> v3: > - Use readsq/writesq on 64-bit architectures (Arnd) > - Detect issue on init instead of 1st transfer > > Changes v3 -> v4: > - Updated link and reviewed tag (Arnd) > --- > .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- > 1 file changed, 58 insertions(+), 12 deletions(-) > > diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c > index 9dac3ca69d57..7661a5cf1883 100644 > --- a/drivers/mtd/nand/raw/cadence-nand-controller.c > +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c > @@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl) > if (cadence_nand_read_bch_caps(cdns_ctrl)) > return -EIO; > > +#ifndef CONFIG_64BIT > + if (cdns_ctrl->caps2.data_dma_width == 8) { > + dev_err(cdns_ctrl->dev, > + "cannot access 64-bit dma on !64-bit architectures"); > + return -EIO; > + } > +#endif > + > /* > * Set IO width access to 8. > * It is because during SW device discovering width access > @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl, > return status; > > if (!cdns_ctrl->caps1->has_dma) { > - int len_in_words = len >> 2; > + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; > + > + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; > > /* read alingment data */ > - ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); > + if (data_dma_width == 4) > + ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); > +#ifdef CONFIG_64BIT > + else > + readsq(cdns_ctrl->io.virt, buf, len_in_words); > +#endif > + > if (sdma_size > len) { > + int read_bytes = (data_dma_width == 4) ? > + len_in_words << 2 : len_in_words << 3; > + > /* read rest data from slave DMA interface if any */ > - ioread32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, > - sdma_size / 4 - len_in_words); > + if (data_dma_width == 4) > + ioread32_rep(cdns_ctrl->io.virt, > + cdns_ctrl->buf, > + sdma_size / 4 - len_in_words); > +#ifdef CONFIG_64BIT > + else > + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, > + sdma_size / 8 - len_in_words); > +#endif > + > /* copy rest of data */ > - memcpy(buf + (len_in_words << 2), cdns_ctrl->buf, > - len - (len_in_words << 2)); > + memcpy(buf + read_bytes, cdns_ctrl->buf, > + len - read_bytes); > } > return 0; > } > @@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, > return status; > > if (!cdns_ctrl->caps1->has_dma) { > - int len_in_words = len >> 2; > + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; > + > + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; > + > + if (data_dma_width == 4) > + iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); > +#ifdef CONFIG_64BIT > + else > + writesq(cdns_ctrl->io.virt, buf, len_in_words); > +#endif > > - iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); > if (sdma_size > len) { > + int written_bytes = (data_dma_width == 4) ? > + len_in_words << 2 : len_in_words << 3; > + > /* copy rest of data */ > - memcpy(cdns_ctrl->buf, buf + (len_in_words << 2), > - len - (len_in_words << 2)); > + memcpy(cdns_ctrl->buf, buf + written_bytes, > + len - written_bytes); > + > /* write all expected by nand controller data */ > - iowrite32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, > - sdma_size / 4 - len_in_words); > + if (data_dma_width == 4) > + iowrite32_rep(cdns_ctrl->io.virt, > + cdns_ctrl->buf, > + sdma_size / 4 - len_in_words); > +#ifdef CONFIG_64BIT > + else > + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, > + sdma_size / 8 - len_in_words); > +#endif > } > > return 0; Thanks, Miquèl
Hi Miquel, On 10/18/22 11:17, Miquel Raynal wrote: > Hi Valentin, > > vkorenblit@sequans.com wrote on Tue, 18 Oct 2022 11:16:31 +0200: > >> 32-bit accesses on 64-bit sdma trigger sdma_err in intr_status register. >> >> Check dma capabilities before reading/writing from/to sdma interface. >> >> Link: https://secure-web.cisco.com/1Zuwps3Jm-Qybygq3UAIg4d4S5heggZX1ow8KENGLYXasfYvc72QPuxCC1kbg9_YPoqVYqfCQVlokpkras6hyjajt6RxKCmlzNhUsTu6vdTgufT8upiLvVnbScXuhDTKV539Fk3pwIluw0CMUbizt16dze_fAdyNKJxwNbEzZIq8DIpD8kK9qUCTdhHSEXza7Ytk_EmwCBawUQFBNNV2CzKBaw-vx5t7gbuvlT1IL9WV4bA3nzUs4NLiN1TV2lBuyA28Duk2i-aouwPb5o3UwDHhHxyCQuGos0F-sSxMREQr2Uj4lgR8lfIpFbk6O8o7J3K2i8rXA4TqUYcRD4BxWWNk3nBHVJxW2oVqX6sjS3Vh32VxOnsoXhttu_3UFm3qziOiukq8jXcvoFPvD6kwJutnujcsJzeGzEBSBfUxSHdgZYFyBbHwqqBC298e3uUV-/https%3A%2F%2Flists.01.org%2Fhyperkitty%2Flist%2Fkbuild-all%40lists.01.org%2Fthread%2F3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B%2F > What happened to the link? I guess there is some security software > interaction here? Should we take the one from your v3? I copy/pasted the link that I received in Arnd's email. Maybe this is better: https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/ Do you want me to do a v5 with it? > >> Signed-off-by: Valentin Korenblit <vkorenblit@sequans.com> >> Reviewed-by: Arnd Bergmann <arnd@arndb.de> >> >> --- >> >> Changes v1 -> v2: >> - Replaced ioread64_rep by cadence_nand_readsq (suggested by Arnd) >> - Replaced iowrite64_rep by cadence_nand_writesq (suggested by Arnd) >> - Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not defined >> >> Changes v2 -> v3: >> - Use readsq/writesq on 64-bit architectures (Arnd) >> - Detect issue on init instead of 1st transfer >> >> Changes v3 -> v4: >> - Updated link and reviewed tag (Arnd) >> --- >> .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- >> 1 file changed, 58 insertions(+), 12 deletions(-) >> >> diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c >> index 9dac3ca69d57..7661a5cf1883 100644 >> --- a/drivers/mtd/nand/raw/cadence-nand-controller.c >> +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c >> @@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl) >> if (cadence_nand_read_bch_caps(cdns_ctrl)) >> return -EIO; >> >> +#ifndef CONFIG_64BIT >> + if (cdns_ctrl->caps2.data_dma_width == 8) { >> + dev_err(cdns_ctrl->dev, >> + "cannot access 64-bit dma on !64-bit architectures"); >> + return -EIO; >> + } >> +#endif >> + >> /* >> * Set IO width access to 8. >> * It is because during SW device discovering width access >> @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl, >> return status; >> >> if (!cdns_ctrl->caps1->has_dma) { >> - int len_in_words = len >> 2; >> + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; >> + >> + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; >> >> /* read alingment data */ >> - ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); >> + if (data_dma_width == 4) >> + ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); >> +#ifdef CONFIG_64BIT >> + else >> + readsq(cdns_ctrl->io.virt, buf, len_in_words); >> +#endif >> + >> if (sdma_size > len) { >> + int read_bytes = (data_dma_width == 4) ? >> + len_in_words << 2 : len_in_words << 3; >> + >> /* read rest data from slave DMA interface if any */ >> - ioread32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, >> - sdma_size / 4 - len_in_words); >> + if (data_dma_width == 4) >> + ioread32_rep(cdns_ctrl->io.virt, >> + cdns_ctrl->buf, >> + sdma_size / 4 - len_in_words); >> +#ifdef CONFIG_64BIT >> + else >> + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, >> + sdma_size / 8 - len_in_words); >> +#endif >> + >> /* copy rest of data */ >> - memcpy(buf + (len_in_words << 2), cdns_ctrl->buf, >> - len - (len_in_words << 2)); >> + memcpy(buf + read_bytes, cdns_ctrl->buf, >> + len - read_bytes); >> } >> return 0; >> } >> @@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, >> return status; >> >> if (!cdns_ctrl->caps1->has_dma) { >> - int len_in_words = len >> 2; >> + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; >> + >> + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; >> + >> + if (data_dma_width == 4) >> + iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); >> +#ifdef CONFIG_64BIT >> + else >> + writesq(cdns_ctrl->io.virt, buf, len_in_words); >> +#endif >> >> - iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); >> if (sdma_size > len) { >> + int written_bytes = (data_dma_width == 4) ? >> + len_in_words << 2 : len_in_words << 3; >> + >> /* copy rest of data */ >> - memcpy(cdns_ctrl->buf, buf + (len_in_words << 2), >> - len - (len_in_words << 2)); >> + memcpy(cdns_ctrl->buf, buf + written_bytes, >> + len - written_bytes); >> + >> /* write all expected by nand controller data */ >> - iowrite32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, >> - sdma_size / 4 - len_in_words); >> + if (data_dma_width == 4) >> + iowrite32_rep(cdns_ctrl->io.virt, >> + cdns_ctrl->buf, >> + sdma_size / 4 - len_in_words); >> +#ifdef CONFIG_64BIT >> + else >> + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, >> + sdma_size / 8 - len_in_words); >> +#endif >> } >> >> return 0; > > Thanks, > Miquèl Best regards, Valentin -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
On Tue, Oct 18, 2022, at 11:20 AM, Valentin Korenblit wrote: > > I copy/pasted the link that I received in Arnd's email. > > Maybe this is better: > > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/ To clarify: my point was about using the official 'Link:' tag in the changelog text rather than having a free-form link. When linking to a mailing list post, the best option is usually one from lore.kernel.org. the lists.01.org link is probably fine if the thread is not archived on lore. Arnd
Hi Valentin, vkorenblit@sequans.com wrote on Tue, 18 Oct 2022 11:20:56 +0200: > Hi Miquel, > > On 10/18/22 11:17, Miquel Raynal wrote: > > Hi Valentin, > > > > vkorenblit@sequans.com wrote on Tue, 18 Oct 2022 11:16:31 +0200: > > > >> 32-bit accesses on 64-bit sdma trigger sdma_err in intr_status register. > >> > >> Check dma capabilities before reading/writing from/to sdma interface. > >> > >> Link: https://secure-web.cisco.com/1Zuwps3Jm-Qybygq3UAIg4d4S5heggZX1ow8KENGLYXasfYvc72QPuxCC1kbg9_YPoqVYqfCQVlokpkras6hyjajt6RxKCmlzNhUsTu6vdTgufT8upiLvVnbScXuhDTKV539Fk3pwIluw0CMUbizt16dze_fAdyNKJxwNbEzZIq8DIpD8kK9qUCTdhHSEXza7Ytk_EmwCBawUQFBNNV2CzKBaw-vx5t7gbuvlT1IL9WV4bA3nzUs4NLiN1TV2lBuyA28Duk2i-aouwPb5o3UwDHhHxyCQuGos0F-sSxMREQr2Uj4lgR8lfIpFbk6O8o7J3K2i8rXA4TqUYcRD4BxWWNk3nBHVJxW2oVqX6sjS3Vh32VxOnsoXhttu_3UFm3qziOiukq8jXcvoFPvD6kwJutnujcsJzeGzEBSBfUxSHdgZYFyBbHwqqBC298e3uUV-/https%3A%2F%2Flists.01.org%2Fhyperkitty%2Flist%2Fkbuild-all%40lists.01.org%2Fthread%2F3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B%2F > > What happened to the link? I guess there is some security software > > interaction here? Should we take the one from your v3? > > I copy/pasted the link that I received in Arnd's email. Actually Arnd's e-mail contains the right link, but you probably have some company software poking in your e-mails and translating external links through your cisco protection. What Arnd probably meant was to use Link: xxx rather than Link to the discussion: xxx because the former has been standardized. > Maybe this is better: > > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/ Yes, this is the right link. > > Do you want me to do a v5 with it? I'll take care of it, thanks. > > > > >> Signed-off-by: Valentin Korenblit <vkorenblit@sequans.com> > >> Reviewed-by: Arnd Bergmann <arnd@arndb.de> > >> > >> --- > >> > >> Changes v1 -> v2: > >> - Replaced ioread64_rep by cadence_nand_readsq (suggested by Arnd) > >> - Replaced iowrite64_rep by cadence_nand_writesq (suggested by Arnd) > >> - Do not try to access 64-bit sdma if __raw_readq/__raw_writeq are not defined > >> > >> Changes v2 -> v3: > >> - Use readsq/writesq on 64-bit architectures (Arnd) > >> - Detect issue on init instead of 1st transfer > >> > >> Changes v3 -> v4: > >> - Updated link and reviewed tag (Arnd) > >> --- > >> .../mtd/nand/raw/cadence-nand-controller.c | 70 +++++++++++++++---- > >> 1 file changed, 58 insertions(+), 12 deletions(-) > >> > >> diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c > >> index 9dac3ca69d57..7661a5cf1883 100644 > >> --- a/drivers/mtd/nand/raw/cadence-nand-controller.c > >> +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c > >> @@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl) > >> if (cadence_nand_read_bch_caps(cdns_ctrl)) > >> return -EIO; > >> >> +#ifndef CONFIG_64BIT > >> + if (cdns_ctrl->caps2.data_dma_width == 8) { > >> + dev_err(cdns_ctrl->dev, > >> + "cannot access 64-bit dma on !64-bit architectures"); > >> + return -EIO; > >> + } > >> +#endif > >> + > >> /* > >> * Set IO width access to 8. > >> * It is because during SW device discovering width access > >> @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl, > >> return status; > >> >> if (!cdns_ctrl->caps1->has_dma) { > >> - int len_in_words = len >> 2; > >> + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; > >> + > >> + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; > >> >> /* read alingment data */ > >> - ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); > >> + if (data_dma_width == 4) > >> + ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); > >> +#ifdef CONFIG_64BIT > >> + else > >> + readsq(cdns_ctrl->io.virt, buf, len_in_words); > >> +#endif > >> + > >> if (sdma_size > len) { > >> + int read_bytes = (data_dma_width == 4) ? > >> + len_in_words << 2 : len_in_words << 3; > >> + > >> /* read rest data from slave DMA interface if any */ > >> - ioread32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, > >> - sdma_size / 4 - len_in_words); > >> + if (data_dma_width == 4) > >> + ioread32_rep(cdns_ctrl->io.virt, > >> + cdns_ctrl->buf, > >> + sdma_size / 4 - len_in_words); > >> +#ifdef CONFIG_64BIT > >> + else > >> + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, > >> + sdma_size / 8 - len_in_words); > >> +#endif > >> + > >> /* copy rest of data */ > >> - memcpy(buf + (len_in_words << 2), cdns_ctrl->buf, > >> - len - (len_in_words << 2)); > >> + memcpy(buf + read_bytes, cdns_ctrl->buf, > >> + len - read_bytes); > >> } > >> return 0; > >> } > >> @@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, > >> return status; > >> >> if (!cdns_ctrl->caps1->has_dma) { > >> - int len_in_words = len >> 2; > >> + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; > >> + > >> + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; > >> + > >> + if (data_dma_width == 4) > >> + iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); > >> +#ifdef CONFIG_64BIT > >> + else > >> + writesq(cdns_ctrl->io.virt, buf, len_in_words); > >> +#endif > >> >> - iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); > >> if (sdma_size > len) { > >> + int written_bytes = (data_dma_width == 4) ? > >> + len_in_words << 2 : len_in_words << 3; > >> + > >> /* copy rest of data */ > >> - memcpy(cdns_ctrl->buf, buf + (len_in_words << 2), > >> - len - (len_in_words << 2)); > >> + memcpy(cdns_ctrl->buf, buf + written_bytes, > >> + len - written_bytes); > >> + > >> /* write all expected by nand controller data */ > >> - iowrite32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, > >> - sdma_size / 4 - len_in_words); > >> + if (data_dma_width == 4) > >> + iowrite32_rep(cdns_ctrl->io.virt, > >> + cdns_ctrl->buf, > >> + sdma_size / 4 - len_in_words); > >> +#ifdef CONFIG_64BIT > >> + else > >> + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, > >> + sdma_size / 8 - len_in_words); > >> +#endif > >> } > >> >> return 0; > > > > Thanks, > > Miquèl > > Best regards, > > Valentin > > -- IMPORTANT NOTICE: > > > > The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. > > > > Thank you. Thanks, Miquèl
Hi Arnd, Valentin, arnd@arndb.de wrote on Tue, 18 Oct 2022 11:23:04 +0200: > On Tue, Oct 18, 2022, at 11:20 AM, Valentin Korenblit wrote: > > > > I copy/pasted the link that I received in Arnd's email. > > > > Maybe this is better: > > > > https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org/thread/3NMACGIM5NDUBPXRT5RTBZON6LQE5A3B/ > > To clarify: my point was about using the official 'Link:' tag > in the changelog text rather than having a free-form link. > > When linking to a mailing list post, the best option > is usually one from lore.kernel.org. the lists.01.org > link is probably fine if the thread is not archived on lore. It is: https://lore.kernel.org/all/b7e5ebb4-0de8-4958-9bc4-fe06ec4c3635@www.fastmail.com/t/ Valentin, can you eventually send a v5 with this link if you agree? Thanks, Miquèl
diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c index 9dac3ca69d57..7661a5cf1883 100644 --- a/drivers/mtd/nand/raw/cadence-nand-controller.c +++ b/drivers/mtd/nand/raw/cadence-nand-controller.c @@ -1184,6 +1184,14 @@ static int cadence_nand_hw_init(struct cdns_nand_ctrl *cdns_ctrl) if (cadence_nand_read_bch_caps(cdns_ctrl)) return -EIO; +#ifndef CONFIG_64BIT + if (cdns_ctrl->caps2.data_dma_width == 8) { + dev_err(cdns_ctrl->dev, + "cannot access 64-bit dma on !64-bit architectures"); + return -EIO; + } +#endif + /* * Set IO width access to 8. * It is because during SW device discovering width access @@ -1882,17 +1890,36 @@ static int cadence_nand_read_buf(struct cdns_nand_ctrl *cdns_ctrl, return status; if (!cdns_ctrl->caps1->has_dma) { - int len_in_words = len >> 2; + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; /* read alingment data */ - ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); + if (data_dma_width == 4) + ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, buf, len_in_words); +#endif + if (sdma_size > len) { + int read_bytes = (data_dma_width == 4) ? + len_in_words << 2 : len_in_words << 3; + /* read rest data from slave DMA interface if any */ - ioread32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size / 4 - len_in_words); + if (data_dma_width == 4) + ioread32_rep(cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size / 4 - len_in_words); +#ifdef CONFIG_64BIT + else + readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif + /* copy rest of data */ - memcpy(buf + (len_in_words << 2), cdns_ctrl->buf, - len - (len_in_words << 2)); + memcpy(buf + read_bytes, cdns_ctrl->buf, + len - read_bytes); } return 0; } @@ -1936,16 +1963,35 @@ static int cadence_nand_write_buf(struct cdns_nand_ctrl *cdns_ctrl, return status; if (!cdns_ctrl->caps1->has_dma) { - int len_in_words = len >> 2; + u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; + + int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3; + + if (data_dma_width == 4) + iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, buf, len_in_words); +#endif - iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); if (sdma_size > len) { + int written_bytes = (data_dma_width == 4) ? + len_in_words << 2 : len_in_words << 3; + /* copy rest of data */ - memcpy(cdns_ctrl->buf, buf + (len_in_words << 2), - len - (len_in_words << 2)); + memcpy(cdns_ctrl->buf, buf + written_bytes, + len - written_bytes); + /* write all expected by nand controller data */ - iowrite32_rep(cdns_ctrl->io.virt, cdns_ctrl->buf, - sdma_size / 4 - len_in_words); + if (data_dma_width == 4) + iowrite32_rep(cdns_ctrl->io.virt, + cdns_ctrl->buf, + sdma_size / 4 - len_in_words); +#ifdef CONFIG_64BIT + else + writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, + sdma_size / 8 - len_in_words); +#endif } return 0;