diff mbox series

[v3,2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

Message ID 20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com
State Accepted
Headers show
Series mtd: rawnand: arasan: Fix clock rate in NV-DDR | expand

Commit Message

Amit Kumar Mahapatra June 28, 2022, 3:48 p.m. UTC 
From: Olga Kitaina <okitain@gmail.com>

According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.

The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.

Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Olga Kitaina <okitain@gmail.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
---
 drivers/mtd/nand/raw/arasan-nand-controller.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Miquel Raynal June 29, 2022, 11:38 a.m. UTC | #1 
On Tue, 2022-06-28 at 15:48:24 UTC, Amit Kumar Mahapatra wrote:
> From: Olga Kitaina <okitain@gmail.com>
> 
> According to the Arasan NAND controller spec, the flash clock rate for SDR
> must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
> CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
> which would result in incorrect behavior for NV-DDR modes 0-4.
> 
> The appropriate clock rate can be calculated from the NV-DDR timing
> parameters as 1/tCK, or for rates measured in picoseconds,
> 10^12 / nand_nvddr_timings->tCK_min.
> 
> Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
> CC: stable@vger.kernel.org # 5.8+
> Signed-off-by: Olga Kitaina <okitain@gmail.com>
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel
diff mbox series

Patch

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index c5264fa223c4..d4121d1243bf 100644
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -1043,7 +1043,13 @@  static int anfc_setup_interface(struct nand_chip *chip, int target,
 				 DQS_BUFF_SEL_OUT(dqs_mode);
 	}
 
-	anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	if (nand_interface_is_sdr(conf)) {
+		anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	} else {
+		/* ONFI timings are defined in picoseconds */
+		anand->clk =  div_u64((u64)NSEC_PER_SEC * 1000,
+				      conf->timings.nvddr.tCK_min);
+	}
 
 	/*
 	 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work