| Message ID | 20220628112731.2041976-3-martin.blumenstingl@googlemail.com |
|---|---|
| State | Changes Requested |
| Headers | show
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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: linux-mtd@lists.infradead.org,
devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org,
tlanger@maxlinear.com,
rtanwar@maxlinear.com,
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Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v1 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum
chip select value
Date: Tue, 28 Jun 2022 13:27:25 +0200
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Content preview: The Intel LGM NAND IP only supports two chip selects:
There's
only two CS and ADDR_SEL register sets. Fix the maximum allowed chip
select
value according to the dt-bindings. Fixes: 2f9cea8eae44f5 ("dt-bindings:
mtd: Add Nand Flash Controller support for Intel LGM SoC") Signed-off-by:
Martin Blumenstingl ---
Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
| 2 + [...]
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|
| Series |
intel-nand-controller: Fixes, cleanups and questions
|
expand
|
diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml index 763ee3e1faf3..04f26196c4c1 100644 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml @@ -51,7 +51,7 @@ patternProperties: properties: reg: minimum: 0 - maximum: 7 + maximum: 1 nand-ecc-mode: true
The Intel LGM NAND IP only supports two chip selects: There's only two CS and ADDR_SEL register sets. Fix the maximum allowed chip select value according to the dt-bindings. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)