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[v2,4/5] spi: dt-bindings: Describe stacked/parallel memories modes

Message ID 20211126163450.394861-5-miquel.raynal@bootlin.com
State Superseded
Delegated to: Ambarus Tudor
Headers show
Series Stacked/parallel memories bindings | expand

Commit Message

Miquel Raynal Nov. 26, 2021, 4:34 p.m. UTC 
Describe two new memories modes:
- A stacked mode when the bus is common but the address space extended
  with an additinals wires.
- A parallel mode with parallel busses accessing parallel flashes where
  the data is spread.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 .../bindings/spi/spi-controller.yaml          | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Rob Herring Dec. 2, 2021, 12:04 a.m. UTC | #1 
On Fri, Nov 26, 2021 at 05:34:49PM +0100, Miquel Raynal wrote:
> Describe two new memories modes:
> - A stacked mode when the bus is common but the address space extended
>   with an additinals wires.
> - A parallel mode with parallel busses accessing parallel flashes where
>   the data is spread.

I don't quite understand why this is in spi-controller.yaml.

Also, please see this series[1].

Rob

[1] https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml
index 556c5ddc39d2..1ceba6c7430d 100644
--- a/Documentation/devicetree/bindings/spi/spi-controller.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml
@@ -162,6 +162,27 @@  patternProperties:
         description:
           Delay, in microseconds, after a write transfer.
 
+      stacked-memories:
+        type: boolean
+        description: Several SPI memories can be wired in stacked mode.
+          This basically means that either a device features several chip
+          selects, or that different devices must be seen as a single
+          bigger chip. This basically doubles (or more) the total address
+          space with only a single additional wire, while still needing
+          to repeat the commands when crossing a chip boundary. XIP is
+          usually not supported in this mode.
+
+      parallel-memories:
+        type: boolean
+        description: Several SPI memories can be wired in parallel mode.
+          The devices are physically on a different buses but will always
+          act synchronously as each data word is spread across the
+          different memories (eg. even bits are stored in one memory, odd
+          bits in the other). This basically doubles the address space and
+          the throughput while greatly complexifying the wiring because as
+          many busses as devices must be wired. XIP is usually not
+          supported in this mode.
+
     required:
       - compatible
       - reg