diff mbox series

[v7,9/9] arm64: dts: rockchip: Enable SFC for Odroid Go Advance

Message ID 20210609141348.19178-5-jon.lin@rock-chips.com
State New
Headers show
Series Add Rockchip SFC(serial flash controller) support | expand

Commit Message

Jon Lin June 9, 2021, 2:13 p.m. UTC
From: Chris Morgan <macromorgan@hotmail.com>

This enables the Rockchip Serial Flash Controller for the Odroid Go
Advance. Note that while the attached SPI NOR flash and the controller
both support quad read mode, only 2 of the required 4 pins are present.
The rx and tx bus width is set to 2 for this reason.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1: None

 .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Chris Morgan June 10, 2021, 5:36 p.m. UTC | #1
On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
> 
> This enables the Rockchip Serial Flash Controller for the Odroid Go
> Advance. Note that while the attached SPI NOR flash and the controller
> both support quad read mode, only 2 of the required 4 pins are present.
> The rx and tx bus width is set to 2 for this reason.
> 
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
> 
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> Changes in v1: None
> 
>  .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> index 49c97f76df77..f78e11dd8447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> @@ -484,6 +484,22 @@
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <108000000>;
> +		spi-rx-bus-width = <2>;
> +		spi-tx-bus-width = <2>;

Note that I am still working with Jon Lin to research this, but it was
found in testing that if I set the tx bus width to 1 the problems I
encountered in earlier are resolved. At this time I do not know if it
is an issue with the driver for the flash controller, or if the NOR, or
board itself has some sort of errata which prevent dual tx from working
correctly. Note that as of right now the flash chip I am using (an
XTX XT25F128B) is not currently supported in mainline, so it's very
possible this is some sort of errata with the chip. It's also possible
that there is something with the board that is interferring with dual
mode TX.  When Jon comes back that he has tested dual mode on the SFC
with a different board/chip I will recommend that we change the tx
bus width here to a 1, and then once the XT25F128B gets mainlined we
can see if someone else has issues with dual tx mode so we can note
that as a problem with the chip. Or maybe there is something weird
with dual tx mode yet on the SFC driver/controller, I don't know yet.
I'm all too happy to work with a Rockchip engineer so things like
this can be determined before we hit mainline. :-)

The XTX25F128B driver is currently awaiting a decision on how to handle
continuation codes, as this chip ID should be using continuation codes,
but doesn't appear to return them when you query for manufacturer ID.
So I should also note in the commit here that the SFC will still be
unusable on the Odroid Go Advance until the XTX25F128B is also
mainlined.

Thank you.

> +	};
> +};
> +
>  &tsadc {
>  	status = "okay";
>  };
> -- 
> 2.17.1
> 
> 
>
Jon Lin June 11, 2021, 2:26 a.m. UTC | #2
Hi Chris

May you attach the XT25F128B device code to me, and I'll try to work it out.

On 6/11/21 1:36 AM, Chris Morgan wrote:
> On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
>> From: Chris Morgan <macromorgan@hotmail.com>
>>
>> This enables the Rockchip Serial Flash Controller for the Odroid Go
>> Advance. Note that while the attached SPI NOR flash and the controller
>> both support quad read mode, only 2 of the required 4 pins are present.
>> The rx and tx bus width is set to 2 for this reason.
>>
>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
>> ---
>>
>> Changes in v7: None
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>> Changes in v1: None
>>
>>   .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>> index 49c97f76df77..f78e11dd8447 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>> @@ -484,6 +484,22 @@
>>   	status = "okay";
>>   };
>>   
>> +&sfc {
>> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
>> +	pinctrl-names = "default";
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +	status = "okay";
>> +
>> +	flash@0 {
>> +		compatible = "jedec,spi-nor";
>> +		reg = <0>;
>> +		spi-max-frequency = <108000000>;
>> +		spi-rx-bus-width = <2>;
>> +		spi-tx-bus-width = <2>;
> Note that I am still working with Jon Lin to research this, but it was
> found in testing that if I set the tx bus width to 1 the problems I
> encountered in earlier are resolved. At this time I do not know if it
> is an issue with the driver for the flash controller, or if the NOR, or
> board itself has some sort of errata which prevent dual tx from working
> correctly. Note that as of right now the flash chip I am using (an
> XTX XT25F128B) is not currently supported in mainline, so it's very
> possible this is some sort of errata with the chip. It's also possible
> that there is something with the board that is interferring with dual
> mode TX.  When Jon comes back that he has tested dual mode on the SFC
> with a different board/chip I will recommend that we change the tx
> bus width here to a 1, and then once the XT25F128B gets mainlined we
> can see if someone else has issues with dual tx mode so we can note
> that as a problem with the chip. Or maybe there is something weird
> with dual tx mode yet on the SFC driver/controller, I don't know yet.
> I'm all too happy to work with a Rockchip engineer so things like
> this can be determined before we hit mainline. :-)
>
> The XTX25F128B driver is currently awaiting a decision on how to handle
> continuation codes, as this chip ID should be using continuation codes,
> but doesn't appear to return them when you query for manufacturer ID.
> So I should also note in the commit here that the SFC will still be
> unusable on the Odroid Go Advance until the XTX25F128B is also
> mainlined.
>
> Thank you.
>
>> +	};
>> +};
>> +
>>   &tsadc {
>>   	status = "okay";
>>   };
>> -- 
>> 2.17.1
>>
>>
>>
>
>
Chris Morgan June 11, 2021, 3:38 a.m. UTC | #3
On Fri, Jun 11, 2021 at 10:26:35AM +0800, Jon Lin wrote:
> Hi Chris
> 
> May you attach the XT25F128B device code to me, and I'll try to work it out.

Sure, here is the patch I am using:

https://patchwork.ozlabs.org/project/linux-mtd/patch/SN6PR06MB5342C82F372F37FB8E21B327A57A9@SN6PR06MB5342.namprd06.prod.outlook.com/

> 
> On 6/11/21 1:36 AM, Chris Morgan wrote:
> > On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> > > From: Chris Morgan <macromorgan@hotmail.com>
> > > 
> > > This enables the Rockchip Serial Flash Controller for the Odroid Go
> > > Advance. Note that while the attached SPI NOR flash and the controller
> > > both support quad read mode, only 2 of the required 4 pins are present.
> > > The rx and tx bus width is set to 2 for this reason.
> > > 
> > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> > > ---
> > > 
> > > Changes in v7: None
> > > Changes in v6: None
> > > Changes in v5: None
> > > Changes in v4: None
> > > Changes in v3: None
> > > Changes in v2: None
> > > Changes in v1: None
> > > 
> > >   .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
> > >   1 file changed, 16 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> > > index 49c97f76df77..f78e11dd8447 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> > > @@ -484,6 +484,22 @@
> > >   	status = "okay";
> > >   };
> > > +&sfc {
> > > +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> > > +	pinctrl-names = "default";
> > > +	#address-cells = <1>;
> > > +	#size-cells = <0>;
> > > +	status = "okay";
> > > +
> > > +	flash@0 {
> > > +		compatible = "jedec,spi-nor";
> > > +		reg = <0>;
> > > +		spi-max-frequency = <108000000>;
> > > +		spi-rx-bus-width = <2>;
> > > +		spi-tx-bus-width = <2>;
> > Note that I am still working with Jon Lin to research this, but it was
> > found in testing that if I set the tx bus width to 1 the problems I
> > encountered in earlier are resolved. At this time I do not know if it
> > is an issue with the driver for the flash controller, or if the NOR, or
> > board itself has some sort of errata which prevent dual tx from working
> > correctly. Note that as of right now the flash chip I am using (an
> > XTX XT25F128B) is not currently supported in mainline, so it's very
> > possible this is some sort of errata with the chip. It's also possible
> > that there is something with the board that is interferring with dual
> > mode TX.  When Jon comes back that he has tested dual mode on the SFC
> > with a different board/chip I will recommend that we change the tx
> > bus width here to a 1, and then once the XT25F128B gets mainlined we
> > can see if someone else has issues with dual tx mode so we can note
> > that as a problem with the chip. Or maybe there is something weird
> > with dual tx mode yet on the SFC driver/controller, I don't know yet.
> > I'm all too happy to work with a Rockchip engineer so things like
> > this can be determined before we hit mainline. :-)
> > 
> > The XTX25F128B driver is currently awaiting a decision on how to handle
> > continuation codes, as this chip ID should be using continuation codes,
> > but doesn't appear to return them when you query for manufacturer ID.
> > So I should also note in the commit here that the SFC will still be
> > unusable on the Odroid Go Advance until the XTX25F128B is also
> > mainlined.
> > 
> > Thank you.
> > 
> > > +	};
> > > +};
> > > +
> > >   &tsadc {
> > >   	status = "okay";
> > >   };
> > > -- 
> > > 2.17.1
> > > 
> > > 
> > > 
> > 
> > 
> 
>
Jon Lin June 11, 2021, 3:54 a.m. UTC | #4
On 6/11/21 11:38 AM, Chris Morgan wrote:
> On Fri, Jun 11, 2021 at 10:26:35AM +0800, Jon Lin wrote:
>> Hi Chris
>>
>> May you attach the XT25F128B device code to me, and I'll try to work it out.
> Sure, here is the patch I am using:
>
> https://patchwork.ozlabs.org/project/linux-mtd/patch/SN6PR06MB5342C82F372F37FB8E21B327A57A9@SN6PR06MB5342.namprd06.prod.outlook.com/

this patch works well in my rk3308 tx-2 rx-2 XT25F128BSSIGU case.

# dd if=/tmp/rand.img of=/dev/mtdblock0 bs=4096 seek=1024
1024+0 records in
1024+0 records out
#
# dd if=/dev/mtd0 of=/tmp/rand1.img bs=4096 skip=1024 count=1024

1024+0 records in
1024+0 records out
#
#
# md5sum /tmp/*.img
83e45a56766168b47e6db1d41b1b403d  /tmp/rand.img
83e45a56766168b47e6db1d41b1b403d  /tmp/rand1.img
#
# dmesg | grep XT25F128BSSIGU
[    0.200738] spi-nor spi3.0: XT25F128BSSIGU (16384 Kbytes)
#

>
>> On 6/11/21 1:36 AM, Chris Morgan wrote:
>>> On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
>>>> From: Chris Morgan <macromorgan@hotmail.com>
>>>>
>>>> This enables the Rockchip Serial Flash Controller for the Odroid Go
>>>> Advance. Note that while the attached SPI NOR flash and the controller
>>>> both support quad read mode, only 2 of the required 4 pins are present.
>>>> The rx and tx bus width is set to 2 for this reason.
>>>>
>>>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>>>> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
>>>> ---
>>>>
>>>> Changes in v7: None
>>>> Changes in v6: None
>>>> Changes in v5: None
>>>> Changes in v4: None
>>>> Changes in v3: None
>>>> Changes in v2: None
>>>> Changes in v1: None
>>>>
>>>>    .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
>>>>    1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>>>> index 49c97f76df77..f78e11dd8447 100644
>>>> --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>>>> +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
>>>> @@ -484,6 +484,22 @@
>>>>    	status = "okay";
>>>>    };
>>>> +&sfc {
>>>> +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
>>>> +	pinctrl-names = "default";
>>>> +	#address-cells = <1>;
>>>> +	#size-cells = <0>;
>>>> +	status = "okay";
>>>> +
>>>> +	flash@0 {
>>>> +		compatible = "jedec,spi-nor";
>>>> +		reg = <0>;
>>>> +		spi-max-frequency = <108000000>;
>>>> +		spi-rx-bus-width = <2>;
>>>> +		spi-tx-bus-width = <2>;
>>> Note that I am still working with Jon Lin to research this, but it was
>>> found in testing that if I set the tx bus width to 1 the problems I
>>> encountered in earlier are resolved. At this time I do not know if it
>>> is an issue with the driver for the flash controller, or if the NOR, or
>>> board itself has some sort of errata which prevent dual tx from working
>>> correctly. Note that as of right now the flash chip I am using (an
>>> XTX XT25F128B) is not currently supported in mainline, so it's very
>>> possible this is some sort of errata with the chip. It's also possible
>>> that there is something with the board that is interferring with dual
>>> mode TX.  When Jon comes back that he has tested dual mode on the SFC
>>> with a different board/chip I will recommend that we change the tx
>>> bus width here to a 1, and then once the XT25F128B gets mainlined we
>>> can see if someone else has issues with dual tx mode so we can note
>>> that as a problem with the chip. Or maybe there is something weird
>>> with dual tx mode yet on the SFC driver/controller, I don't know yet.
>>> I'm all too happy to work with a Rockchip engineer so things like
>>> this can be determined before we hit mainline. :-)
>>>
>>> The XTX25F128B driver is currently awaiting a decision on how to handle
>>> continuation codes, as this chip ID should be using continuation codes,
>>> but doesn't appear to return them when you query for manufacturer ID.
>>> So I should also note in the commit here that the SFC will still be
>>> unusable on the Odroid Go Advance until the XTX25F128B is also
>>> mainlined.
>>>
>>> Thank you.
>>>
>>>> +	};
>>>> +};
>>>> +
>>>>    &tsadc {
>>>>    	status = "okay";
>>>>    };
>>>> -- 
>>>> 2.17.1
>>>>
>>>>
>>>>
>>>
>>
>
>
Chris Morgan June 11, 2021, 2:08 p.m. UTC | #5
On Fri, Jun 11, 2021 at 11:54:09AM +0800, Jon Lin wrote:
> 
> On 6/11/21 11:38 AM, Chris Morgan wrote:
> > On Fri, Jun 11, 2021 at 10:26:35AM +0800, Jon Lin wrote:
> > > Hi Chris
> > > 
> > > May you attach the XT25F128B device code to me, and I'll try to work it out.
> > Sure, here is the patch I am using:
> > 
> > https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Flinux-mtd%2Fpatch%2FSN6PR06MB5342C82F372F37FB8E21B327A57A9%40SN6PR06MB5342.namprd06.prod.outlook.com%2F&amp;data=04%7C01%7C%7Cc6a3139cc88d47d229cc08d92c8c9354%7C84df9e7fe9f640afb435aaaaaaaaaaaa%7C1%7C0%7C637589804539399553%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=zdYTqTXhEYI6%2Brq8W4msXZcfDW2XMWzP%2BvtDYMOVsrw%3D&amp;reserved=0
> 
> this patch works well in my rk3308 tx-2 rx-2 XT25F128BSSIGU case.

That answers the question then. There must be some board level issue
specific to the Odroid Go Advance. I'll test your latest v8 patches
to confirm again but I think I'll need to update the TX lanes here
to 1 instead of 2. Otherwise, things seem to work fine now.

Thank you.

> 
> # dd if=/tmp/rand.img of=/dev/mtdblock0 bs=4096 seek=1024
> 1024+0 records in
> 1024+0 records out
> #
> # dd if=/dev/mtd0 of=/tmp/rand1.img bs=4096 skip=1024 count=1024
> 
> 1024+0 records in
> 1024+0 records out
> #
> #
> # md5sum /tmp/*.img
> 83e45a56766168b47e6db1d41b1b403d  /tmp/rand.img
> 83e45a56766168b47e6db1d41b1b403d  /tmp/rand1.img
> #
> # dmesg | grep XT25F128BSSIGU
> [    0.200738] spi-nor spi3.0: XT25F128BSSIGU (16384 Kbytes)
> #
> 
> > 
> > > On 6/11/21 1:36 AM, Chris Morgan wrote:
> > > > On Wed, Jun 09, 2021 at 10:13:48PM +0800, Jon Lin wrote:
> > > > > From: Chris Morgan <macromorgan@hotmail.com>
> > > > > 
> > > > > This enables the Rockchip Serial Flash Controller for the Odroid Go
> > > > > Advance. Note that while the attached SPI NOR flash and the controller
> > > > > both support quad read mode, only 2 of the required 4 pins are present.
> > > > > The rx and tx bus width is set to 2 for this reason.
> > > > > 
> > > > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > > > > Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> > > > > ---
> > > > > 
> > > > > Changes in v7: None
> > > > > Changes in v6: None
> > > > > Changes in v5: None
> > > > > Changes in v4: None
> > > > > Changes in v3: None
> > > > > Changes in v2: None
> > > > > Changes in v1: None
> > > > > 
> > > > >    .../boot/dts/rockchip/rk3326-odroid-go2.dts      | 16 ++++++++++++++++
> > > > >    1 file changed, 16 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> > > > > index 49c97f76df77..f78e11dd8447 100644
> > > > > --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> > > > > +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
> > > > > @@ -484,6 +484,22 @@
> > > > >    	status = "okay";
> > > > >    };
> > > > > +&sfc {
> > > > > +	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> > > > > +	pinctrl-names = "default";
> > > > > +	#address-cells = <1>;
> > > > > +	#size-cells = <0>;
> > > > > +	status = "okay";
> > > > > +
> > > > > +	flash@0 {
> > > > > +		compatible = "jedec,spi-nor";
> > > > > +		reg = <0>;
> > > > > +		spi-max-frequency = <108000000>;
> > > > > +		spi-rx-bus-width = <2>;
> > > > > +		spi-tx-bus-width = <2>;
> > > > Note that I am still working with Jon Lin to research this, but it was
> > > > found in testing that if I set the tx bus width to 1 the problems I
> > > > encountered in earlier are resolved. At this time I do not know if it
> > > > is an issue with the driver for the flash controller, or if the NOR, or
> > > > board itself has some sort of errata which prevent dual tx from working
> > > > correctly. Note that as of right now the flash chip I am using (an
> > > > XTX XT25F128B) is not currently supported in mainline, so it's very
> > > > possible this is some sort of errata with the chip. It's also possible
> > > > that there is something with the board that is interferring with dual
> > > > mode TX.  When Jon comes back that he has tested dual mode on the SFC
> > > > with a different board/chip I will recommend that we change the tx
> > > > bus width here to a 1, and then once the XT25F128B gets mainlined we
> > > > can see if someone else has issues with dual tx mode so we can note
> > > > that as a problem with the chip. Or maybe there is something weird
> > > > with dual tx mode yet on the SFC driver/controller, I don't know yet.
> > > > I'm all too happy to work with a Rockchip engineer so things like
> > > > this can be determined before we hit mainline. :-)
> > > > 
> > > > The XTX25F128B driver is currently awaiting a decision on how to handle
> > > > continuation codes, as this chip ID should be using continuation codes,
> > > > but doesn't appear to return them when you query for manufacturer ID.
> > > > So I should also note in the commit here that the SFC will still be
> > > > unusable on the Odroid Go Advance until the XTX25F128B is also
> > > > mainlined.
> > > > 
> > > > Thank you.
> > > > 
> > > > > +	};
> > > > > +};
> > > > > +
> > > > >    &tsadc {
> > > > >    	status = "okay";
> > > > >    };
> > > > > -- 
> > > > > 2.17.1
> > > > > 
> > > > > 
> > > > > 
> > > > 
> > > 
> > 
> > 
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index 49c97f76df77..f78e11dd8447 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -484,6 +484,22 @@ 
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <108000000>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+	};
+};
+
 &tsadc {
 	status = "okay";
 };