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Mon, 08 Mar 2021 06:30:17 +0000 IronPort-SDR: h3LkEFvDZUJj18vUQPQGSAgTQEQS5GbaKPuHd3yUd9d6Ohl/sV2gqsk7amJJM/BH5IU/y1m/SB QTz3qex6AqjA== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="188084483" X-IronPort-AV: E=Sophos;i="5.81,231,1610438400"; d="scan'208";a="188084483" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2021 22:28:19 -0800 IronPort-SDR: sRnFPwk1gbxDBaqBE17h22KiFsq+QEDcDfEQboZp0Ln+qUDtQScNalSzH5OaP3IBuI8ofyjqIX edJbLKDFsuuQ== X-IronPort-AV: E=Sophos;i="5.81,231,1610438400"; d="scan'208";a="409181953" Received: from twinkler-lnx.jer.intel.com ([10.12.91.138]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2021 22:28:16 -0800 From: Tomas Winkler To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi Cc: Alexander Usyskin , Vitaly Lubart , linux-mtd@lists.infradead.org, intel-gfx@lists.freedesktop.org, Tomas Winkler , Lucas De Marchi Subject: [RFC PATCH 05/10 v2] drm/i915/spi: implement spi access functions Date: Mon, 8 Mar 2021 08:27:43 +0200 Message-Id: <20210308062748.208017-6-tomas.winkler@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210308062748.208017-1-tomas.winkler@intel.com> References: <20210308062748.208017-1-tomas.winkler@intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_063012_924504_1E773025 X-CRM114-Status: GOOD ( 17.66 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.4 on casper.infradead.org summary: Content analysis details: (-4.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [134.134.136.24 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [134.134.136.24 listed in wl.mailspike.net] 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Implement spi_read() spi_erase() spi_write() functions. Cc: Lucas De Marchi Cc: Rodrigo Vivi Signed-off-by: Tomas Winkler Co-developed-by: Alexander Usyskin Signed-off-by: Alexander Usyskin Co-developed-by: Vitaly Lubart Signed-off-by: Vitaly Lubart --- V2: 1. Rebase drivers/gpu/drm/i915/spi/i915_spi.c | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/i915_spi.c b/drivers/gpu/drm/i915/spi/i915_spi.c index a1e7171d05db..df6a461d520d 100644 --- a/drivers/gpu/drm/i915/spi/i915_spi.c +++ b/drivers/gpu/drm/i915/spi/i915_spi.c @@ -9,7 +9,10 @@ #include #include #include +#include +#include #include +#include #include struct i915_spi { @@ -83,6 +86,33 @@ static inline u32 spi_read32(struct i915_spi *spi, u32 address) return ioread32(base + SPI_TRIGGER_REG); } +static inline u64 spi_read64(struct i915_spi *spi, u32 address) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + return readq(base + SPI_TRIGGER_REG); +} + +static void spi_write32(struct i915_spi *spi, u32 address, u32 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + iowrite32(data, base + SPI_TRIGGER_REG); +} + +static void spi_write64(struct i915_spi *spi, u32 address, u64 data) +{ + void __iomem *base = spi->base; + + iowrite32(address, base + SPI_ADDRESS_REG); + + writeq(data, base + SPI_TRIGGER_REG); +} + static int spi_get_access_map(struct i915_spi *spi) { u32 flmap1; @@ -139,6 +169,113 @@ static int i915_spi_is_valid(struct i915_spi *spi) return 0; } +__maybe_unused +static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from) +{ + unsigned int i; + + for (i = 0; i < spi->nregions; i++) { + if ((spi->regions[i].offset + spi->regions[i].size - 1) > from && + spi->regions[i].offset <= from && + spi->regions[i].size != 0) + break; + } + + return i; +} + +__maybe_unused +static ssize_t spi_write(struct i915_spi *spi, u8 region, + loff_t to, size_t len, const unsigned char *buf) +{ + size_t i; + size_t len8; + + spi_set_region_id(spi, region); + + len8 = ALIGN_DOWN(len, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data; + + memcpy(&data, &buf[i], sizeof(u64)); + spi_write64(spi, to + i, data); + if (spi_error(spi)) + return -EIO; + } + + if (len8 != len) { /* caller ensure that write size is at least u32 */ + u32 data; + + memcpy(&data, &buf[i], sizeof(u32)); + spi_write32(spi, to + len8, data); + if (spi_error(spi)) + return -EIO; + } + + return len; +} + +__maybe_unused +static ssize_t spi_read(struct i915_spi *spi, u8 region, + loff_t from, size_t len, unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + + spi_set_region_id(spi, region); + + len8 = ALIGN_DOWN(len, sizeof(u64)); + for (i = 0; i < len8; i += sizeof(u64)) { + u64 data = spi_read64(spi, from + i); + + if (spi_error(spi)) + return -EIO; + + memcpy(&buf[i], &data, sizeof(data)); + } + + len4 = len - len8; + if (len4 >= sizeof(u32)) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, sizeof(data)); + i += sizeof(u32); + len4 -= sizeof(u32); + } + + if (len4 > 0) { + u32 data = spi_read32(spi, from + i); + + if (spi_error(spi)) + return -EIO; + memcpy(&buf[i], &data, len4); + } + + return len; +} + +__maybe_unused +static ssize_t +spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64 *fail_addr) +{ + u64 i; + const u32 block = 0x10; + void __iomem *base = spi->base; + + for (i = 0; i < len; i += SZ_4K) { + iowrite32(from + i, base + SPI_ADDRESS_REG); + iowrite32(region << 24 | block, base + SPI_ERASE_REG); + /* Since the writes are via sguint + * we cannot do back to back erases. + */ + msleep(50); + } + return len; +} + static int i915_spi_init(struct i915_spi *spi, struct device *device) { int ret;