@@ -237,10 +237,6 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
u16 clock;
u8 w0, w1, w2, w3, w4;
- unsigned long chipsize; /* MiB */
- u8 tbits, col_bits, col_size, row_bits, row_bsize;
- u32 val;
-
nand_controller_init(&b47n->base);
b47n->base.ops = &bcm47xxnflash_ops;
b47n->nand_chip.controller = &b47n->base;
@@ -274,32 +270,9 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
err = nand_scan(&b47n->nand_chip, 1);
if (err) {
pr_err("Could not scan NAND flash: %d\n", err);
- goto exit;
- }
-
- /* Configure FLASH */
- chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20;
- tbits = ffs(chipsize); /* find first bit set */
- if (!tbits || tbits != fls(chipsize)) {
- pr_err("Invalid flash size: 0x%lX\n", chipsize);
- err = -ENOTSUPP;
- goto exit;
- }
- tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
-
- col_bits = b47n->nand_chip.page_shift + 1;
- col_size = (col_bits + 7) / 8;
-
- row_bits = tbits - col_bits + 1;
- row_bsize = (row_bits + 7) / 8;
-
- val = CONF_ROW_BYTES(row_bsize) | CONF_COL_BYTES(col_size) |
- CONF_MAGIC_BIT;
- bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
-
-exit:
- if (err)
bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
~BCMA_CC_4706_FLASHSCFG_NF1);
+ }
+
return err;
}
The row and column sizes are now set as part of the exec_op() procedure and adjusted to match the requested number of address cycles. No need to set them in the init() function since those values will be overwritten anyway. As for the other sanity check that was done on the chip size, I don't think it's really needed. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> --- .../mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c | 31 ++----------------- 1 file changed, 2 insertions(+), 29 deletions(-)