From patchwork Wed Dec 2 03:59:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1409293 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=QWjTyUbo; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cm50v1hlyz9sRK for ; Wed, 2 Dec 2020 15:03:05 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=LSxm8xuaV7Uj/sD+mSDnvUTtnqXKG4TRxOdwEJ7jlLU=; b=QWjTyUboHieNvBjbzUgVZ/jLfs EV2+nS3gggpIYYkS53fShkqOVNF50mT+ALCHNRNeYaOk896JD8NSAq3YXzQrW3pQ4vgG5d+Oqr3lq JXsK7vR8BBL/1oRhnQbHZhxxrfiLAmfq8fBVB10/bZOgrG8eNTrWUJDFq165ytFyxgbg161b6yRlH Z2YJQMxxhbQvB0j0qRZCBywsWQqjMkZ3xpcLHmnXjOdBmf1ROMrRTigTJOknkbVfnWRybs/HLv4c7 74X90aK8D2gYjBUz553Ah6WH8Mp3OHs3ppwN277c1OXKXuQ9WgmEYBqySNH/i1PmPQXBzdfFS/db3 zQaZR/Yw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kkJKW-0003Qy-5l; Wed, 02 Dec 2020 04:01:24 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kkJKS-0003QI-NO for linux-mtd@lists.infradead.org; Wed, 02 Dec 2020 04:01:22 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4Cm4y131Xvzhlfs; Wed, 2 Dec 2020 12:00:41 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.487.0; Wed, 2 Dec 2020 12:00:54 +0800 From: Yicong Yang To: , , Subject: [PATCH] mtd: spi-nor: macronix: Add post bfpt fixup for mx25u51245g Date: Wed, 2 Dec 2020 11:59:12 +0800 Message-ID: <1606881552-41659-1-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201201_230121_016942_5B1E7FEC X-CRM114-Status: GOOD ( 14.77 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.32 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.32 listed in list.dnswl.org] 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vigneshr@ti.com, prime.zeng@huawei.com, richard@nod.at, linuxarm@huawei.com, yangyicong@hisilicon.com, miquel.raynal@bootlin.com Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The 64MB MX66U51235F's BFPT_WORD(1) declares BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 and it doesn't provide a 4BAIT table, so the address width will be set to 3-byte by default after parsing BFPT, which will make the upper memory region unusable. As the MX66U51235F shares the same JEDEC ID with MX25U51245G and is identified to MX25U51245G, add a post bfpt fix hook to correct the address width in MX25U51245G's entry will solve this issue. It won't affect MX25U51245G which also use 4-byte address width and the address width will be valided when parsing its 4BAIT table. Signed-off-by: Yicong Yang --- drivers/mtd/spi-nor/macronix.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 9203aba..2b9065c 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -33,6 +33,36 @@ static struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, }; +static int +mx66u51235f_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + /* + * The 64MB MX66U51235F's BFPT_WORD(1) declares + * BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 and it doesn't provide + * a 4BAIT table, so the address width will be set to + * 3-byte by default after parsing BFPT, which will make + * the upper memory region unusable. + * + * As the MX66U51235F shares the same JEDEC ID with + * MX25U51245G and is identified to MX25U51245G, add a + * post bfpt fix hook to correct the address width in + * MX25U51245G's entry will solve this issue. It won't + * affect MX25U51245G which also use 4-byte address + * width and the address width will be valided when + * parsing its 4BAIT table. + */ + nor->addr_width = 4; + + return 0; +} + +static struct spi_nor_fixups mx66u51235f_fixups = { + .post_bfpt = mx66u51235f_post_bfpt_fixups, +}; + static const struct flash_info macronix_parts[] = { /* Macronix */ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, @@ -68,7 +98,8 @@ static const struct flash_info macronix_parts[] = { SECT_4K | SPI_NOR_4B_OPCODES) }, { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) + .fixups = &mx66u51235f_fixups }, { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },