| Message ID | 1589282819-42358-2-git-send-email-yangyicong@hisilicon.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | Add support to Disable the flash quad mode | expand |
Hi Yicong, You generally shouldn't mark a series as "RFC" if you intend it to get merged in. On 12/05/20 07:26PM, Yicong Yang wrote: > Previous we didn't provide a way to disable the flash's quad mode. > Which means we cannot do some cleanup works when to remove or > poweroff the flash, like what set 4-byte address mode does in > spi_nor_restore(). > > Add the capability to disable the flash quad mode, by introducing > an enable flag in the flash parameters quad_enable() hooks and > related functions. > > Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> > --- > drivers/mtd/spi-nor/core.c | 53 ++++++++++++++++++++++++++++++++-------------- > drivers/mtd/spi-nor/core.h | 8 +++---- > 2 files changed, 41 insertions(+), 20 deletions(-) Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Nits below. > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index cc68ea8..72e8d8b 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -1907,15 +1907,17 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > } > > /** > - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status > + * spi_nor_sr1_bit6_quad_enable() - Set/Unset the Quad Enable BIT(6) in the > + * Status > * Register 1. The "Register 1" should be on the same line as the "Status above". > * @nor: pointer to a 'struct spi_nor' > + * @enable: true to enter quad mode. false to leave quad mode. > * > * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > +int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable) > { > int ret; > > @@ -1923,45 +1925,59 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) > + if ((enable && (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) || > + !(enable || (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6))) I still think writing it as: (!enable && !(nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) is slightly more readable. But maybe it's just me so this is OK I guess. > return 0; > > - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > + if (enable) > + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > + else > + nor->bouncebuf[0] &= ~SR1_QUAD_EN_BIT6; > > return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); > } > > /** > - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status > + * spi_nor_sr2_bit1_quad_enable() - set/unset the Quad Enable BIT(1) in the > + * Status > * Register 2. The "Register 2" should be on the same line as the "Status above". > * @nor: pointer to a 'struct spi_nor'. > + * @enable: true to enter quad mode. false to leave quad mode. > * > * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) > +int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable) > { > int ret; [...] > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 6f2f6b2..719a31d 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -219,7 +219,7 @@ struct spi_nor_flash_parameter { > > struct spi_nor_erase_map erase_map; > > - int (*quad_enable)(struct spi_nor *nor); > + int (*quad_enable)(struct spi_nor *nor, bool enable); Update the comment above reflecting that @quad_enable "enables/disables SPI NOR quad mode". > int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); > u32 (*convert_addr)(struct spi_nor *nor, u32 addr); > int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
Hi Pratyush, Thanks for your review. I'll modify Patch 1 and 2 and send a formal serie. Regards, Yicong On 2020/6/15 18:53, Pratyush Yadav wrote: > Hi Yicong, > > You generally shouldn't mark a series as "RFC" if you intend it to get > merged in. > > On 12/05/20 07:26PM, Yicong Yang wrote: >> Previous we didn't provide a way to disable the flash's quad mode. >> Which means we cannot do some cleanup works when to remove or >> poweroff the flash, like what set 4-byte address mode does in >> spi_nor_restore(). >> >> Add the capability to disable the flash quad mode, by introducing >> an enable flag in the flash parameters quad_enable() hooks and >> related functions. >> >> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> >> --- >> drivers/mtd/spi-nor/core.c | 53 ++++++++++++++++++++++++++++++++-------------- >> drivers/mtd/spi-nor/core.h | 8 +++---- >> 2 files changed, 41 insertions(+), 20 deletions(-) > Reviewed-by: Pratyush Yadav <p.yadav@ti.com> > > Nits below. > >> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c >> index cc68ea8..72e8d8b 100644 >> --- a/drivers/mtd/spi-nor/core.c >> +++ b/drivers/mtd/spi-nor/core.c >> @@ -1907,15 +1907,17 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) >> } >> >> /** >> - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status >> + * spi_nor_sr1_bit6_quad_enable() - Set/Unset the Quad Enable BIT(6) in the >> + * Status >> * Register 1. > The "Register 1" should be on the same line as the "Status above". > >> * @nor: pointer to a 'struct spi_nor' >> + * @enable: true to enter quad mode. false to leave quad mode. >> * >> * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. >> * >> * Return: 0 on success, -errno otherwise. >> */ >> -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) >> +int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable) >> { >> int ret; >> >> @@ -1923,45 +1925,59 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) >> if (ret) >> return ret; >> >> - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) >> + if ((enable && (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) || >> + !(enable || (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6))) > I still think writing it as: > > (!enable && !(nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) > > is slightly more readable. But maybe it's just me so this is OK I guess. > >> return 0; >> >> - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; >> + if (enable) >> + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; >> + else >> + nor->bouncebuf[0] &= ~SR1_QUAD_EN_BIT6; >> >> return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); >> } >> >> /** >> - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status >> + * spi_nor_sr2_bit1_quad_enable() - set/unset the Quad Enable BIT(1) in the >> + * Status >> * Register 2. > The "Register 2" should be on the same line as the "Status above". > >> * @nor: pointer to a 'struct spi_nor'. >> + * @enable: true to enter quad mode. false to leave quad mode. >> * >> * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. >> * >> * Return: 0 on success, -errno otherwise. >> */ >> -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) >> +int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable) >> { >> int ret; > [...] >> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h >> index 6f2f6b2..719a31d 100644 >> --- a/drivers/mtd/spi-nor/core.h >> +++ b/drivers/mtd/spi-nor/core.h >> @@ -219,7 +219,7 @@ struct spi_nor_flash_parameter { >> >> struct spi_nor_erase_map erase_map; >> >> - int (*quad_enable)(struct spi_nor *nor); >> + int (*quad_enable)(struct spi_nor *nor, bool enable); > Update the comment above reflecting that @quad_enable "enables/disables > SPI NOR quad mode". > >> int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); >> u32 (*convert_addr)(struct spi_nor *nor, u32 addr); >> int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index cc68ea8..72e8d8b 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1907,15 +1907,17 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) } /** - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status + * spi_nor_sr1_bit6_quad_enable() - Set/Unset the Quad Enable BIT(6) in the + * Status * Register 1. * @nor: pointer to a 'struct spi_nor' + * @enable: true to enter quad mode. false to leave quad mode. * * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. * * Return: 0 on success, -errno otherwise. */ -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) +int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable) { int ret; @@ -1923,45 +1925,59 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) if (ret) return ret; - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) + if ((enable && (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) || + !(enable || (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6))) return 0; - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; + if (enable) + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; + else + nor->bouncebuf[0] &= ~SR1_QUAD_EN_BIT6; return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); } /** - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status + * spi_nor_sr2_bit1_quad_enable() - set/unset the Quad Enable BIT(1) in the + * Status * Register 2. * @nor: pointer to a 'struct spi_nor'. + * @enable: true to enter quad mode. false to leave quad mode. * * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. * * Return: 0 on success, -errno otherwise. */ -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) +int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable) { int ret; if (nor->flags & SNOR_F_NO_READ_CR) - return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); + return spi_nor_write_16bit_cr_and_check(nor, + enable ? SR2_QUAD_EN_BIT1 : 0); ret = spi_nor_read_cr(nor, nor->bouncebuf); if (ret) return ret; - if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) + if ((enable && (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)) || + !(enable || (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1))) return 0; nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; + if (enable) + nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; + else + nor->bouncebuf[0] &= ~SR2_QUAD_EN_BIT1; + return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); } /** - * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. + * spi_nor_sr2_bit7_quad_enable() - set/unset QE bit in Status Register 2. * @nor: pointer to a 'struct spi_nor' + * @enable: true to enter quad mode. false to leave quad mode. * * Set the Quad Enable (QE) bit in the Status Register 2. * @@ -1971,7 +1987,7 @@ int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) * * Return: 0 on success, -errno otherwise. */ -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) +int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable) { u8 *sr2 = nor->bouncebuf; int ret; @@ -1981,11 +1997,15 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) ret = spi_nor_read_sr2(nor, sr2); if (ret) return ret; - if (*sr2 & SR2_QUAD_EN_BIT7) + if ((enable && (*sr2 & SR2_QUAD_EN_BIT7)) || + !(enable || (*sr2 & SR2_QUAD_EN_BIT7))) return 0; /* Update the Quad Enable bit. */ - *sr2 |= SR2_QUAD_EN_BIT7; + if (enable) + *sr2 |= SR2_QUAD_EN_BIT7; + else + *sr2 &= ~SR2_QUAD_EN_BIT7; ret = spi_nor_write_sr2(nor, sr2); if (ret) @@ -2898,12 +2918,13 @@ static int spi_nor_init_params(struct spi_nor *nor) } /** - * spi_nor_quad_enable() - enable Quad I/O if needed. + * spi_nor_quad_enable() - enable/disable Quad I/O if needed. * @nor: pointer to a 'struct spi_nor' + * @enable: true to enable quad mode. false to disable. * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_quad_enable(struct spi_nor *nor) +static int spi_nor_quad_enable(struct spi_nor *nor, bool enable) { if (!nor->params->quad_enable) return 0; @@ -2912,7 +2933,7 @@ static int spi_nor_quad_enable(struct spi_nor *nor) spi_nor_get_protocol_width(nor->write_proto) == 4)) return 0; - return nor->params->quad_enable(nor); + return nor->params->quad_enable(nor, enable); } /** @@ -2936,7 +2957,7 @@ static int spi_nor_init(struct spi_nor *nor) { int err; - err = spi_nor_quad_enable(nor); + err = spi_nor_quad_enable(nor, true); if (err) { dev_dbg(nor->dev, "quad mode not supported\n"); return err; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 6f2f6b2..719a31d 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -219,7 +219,7 @@ struct spi_nor_flash_parameter { struct spi_nor_erase_map erase_map; - int (*quad_enable)(struct spi_nor *nor); + int (*quad_enable)(struct spi_nor *nor, bool enable); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); u32 (*convert_addr)(struct spi_nor *nor, u32 addr); int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); @@ -406,9 +406,9 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor); void spi_nor_unlock_and_unprep(struct spi_nor *nor); -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); +int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable); +int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable); +int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor, bool enable); int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
Previous we didn't provide a way to disable the flash's quad mode. Which means we cannot do some cleanup works when to remove or poweroff the flash, like what set 4-byte address mode does in spi_nor_restore(). Add the capability to disable the flash quad mode, by introducing an enable flag in the flash parameters quad_enable() hooks and related functions. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> --- drivers/mtd/spi-nor/core.c | 53 ++++++++++++++++++++++++++++++++-------------- drivers/mtd/spi-nor/core.h | 8 +++---- 2 files changed, 41 insertions(+), 20 deletions(-)