diff mbox series

[3/4] ARM: dts: r8a77470: Add QSPI support

Message ID 1541075705-1333-4-git-send-email-fabrizio.castro@bp.renesas.com
State Not Applicable
Headers show
Series Add QSPI flash support to iwg23s | expand

Commit Message

Fabrizio Castro Nov. 1, 2018, 12:35 p.m. UTC
Add QSPI[01] support to the RZ/G1C SoC specific device tree.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Simon Horman Nov. 2, 2018, 11:49 a.m. UTC | #1
On Thu, Nov 01, 2018 at 12:35:04PM +0000, Fabrizio Castro wrote:
> Add QSPI[01] support to the RZ/G1C SoC specific device tree.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
>  arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> index e6407e5..04a8877 100644
> --- a/arch/arm/boot/dts/r8a77470.dtsi
> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> @@ -20,6 +20,8 @@
>  		i2c2 = &i2c2;
>  		i2c3 = &i2c3;
>  		i2c4 = &i2c4;
> +		spi0 = &qspi0;
> +		spi1 = &qspi1;
>  	};

Geert can comment but I believe we are moving away from using aliases
in this way and that it would be best if the above hunk was dropped
from this patch.

https://patchwork.kernel.org/patch/10644159/

The rest of the patch looks fine to me.

>  
>  	cpus {
> @@ -460,6 +462,38 @@
>  			status = "disabled";
>  		};
>  
> +		qspi0: spi@e6b10000 {
> +			compatible = "renesas,qspi-r8a77470", "renesas,qspi";
> +			reg = <0 0xe6b10000 0 0x2c>;
> +			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 918>;
> +			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
> +			       <&dmac1 0x17>, <&dmac1 0x18>;
> +			dma-names = "tx", "rx", "tx", "rx";
> +			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			resets = <&cpg 918>;
> +			status = "disabled";
> +		};
> +
> +		qspi1: spi@ee200000 {
> +			compatible = "renesas,qspi-r8a77470", "renesas,qspi";
> +			reg = <0 0xee200000 0 0x2c>;
> +			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 917>;
> +			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
> +			       <&dmac1 0xd1>, <&dmac1 0xd2>;
> +			dma-names = "tx", "rx", "tx", "rx";
> +			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
> +			num-cs = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			resets = <&cpg 917>;
> +			status = "disabled";
> +		};
> +
>  		scif0: serial@e6e60000 {
>  			compatible = "renesas,scif-r8a77470",
>  				     "renesas,rcar-gen2-scif", "renesas,scif";
> -- 
> 2.7.4
>
Fabrizio Castro Nov. 8, 2018, 10:21 a.m. UTC | #2
Hello Simon,

Thank you for your feedback!

> From: Simon Horman <horms@verge.net.au>
> Sent: 02 November 2018 11:50
> Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
>
> On Thu, Nov 01, 2018 at 12:35:04PM +0000, Fabrizio Castro wrote:
> > Add QSPI[01] support to the RZ/G1C SoC specific device tree.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > ---
> >  arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > index e6407e5..04a8877 100644
> > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > @@ -20,6 +20,8 @@
> >  i2c2 = &i2c2;
> >  i2c3 = &i2c3;
> >  i2c4 = &i2c4;
> > +spi0 = &qspi0;
> > +spi1 = &qspi1;
> >  };
>
> Geert can comment but I believe we are moving away from using aliases
> in this way and that it would be best if the above hunk was dropped
> from this patch.
>
> https://patchwork.kernel.org/patch/10644159/

Geert, what do you want me to do here?

Thanks,
Fab

>
> The rest of the patch looks fine to me.
>
> >
> >  cpus {
> > @@ -460,6 +462,38 @@
> >  status = "disabled";
> >  };
> >
> > +qspi0: spi@e6b10000 {
> > +compatible = "renesas,qspi-r8a77470", "renesas,qspi";
> > +reg = <0 0xe6b10000 0 0x2c>;
> > +interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 918>;
> > +dmas = <&dmac0 0x17>, <&dmac0 0x18>,
> > +       <&dmac1 0x17>, <&dmac1 0x18>;
> > +dma-names = "tx", "rx", "tx", "rx";
> > +power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
> > +num-cs = <1>;
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +resets = <&cpg 918>;
> > +status = "disabled";
> > +};
> > +
> > +qspi1: spi@ee200000 {
> > +compatible = "renesas,qspi-r8a77470", "renesas,qspi";
> > +reg = <0 0xee200000 0 0x2c>;
> > +interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
> > +clocks = <&cpg CPG_MOD 917>;
> > +dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
> > +       <&dmac1 0xd1>, <&dmac1 0xd2>;
> > +dma-names = "tx", "rx", "tx", "rx";
> > +power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
> > +num-cs = <1>;
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +resets = <&cpg 917>;
> > +status = "disabled";
> > +};
> > +
> >  scif0: serial@e6e60000 {
> >  compatible = "renesas,scif-r8a77470",
> >       "renesas,rcar-gen2-scif", "renesas,scif";
> > --
> > 2.7.4
> >



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Geert Uytterhoeven Nov. 8, 2018, 10:24 a.m. UTC | #3
Hi Fabrizio,

On Thu, Nov 8, 2018 at 11:22 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> > From: Simon Horman <horms@verge.net.au>
> > Sent: 02 November 2018 11:50
> > Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
> >
> > On Thu, Nov 01, 2018 at 12:35:04PM +0000, Fabrizio Castro wrote:
> > > Add QSPI[01] support to the RZ/G1C SoC specific device tree.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > ---
> > >  arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
> > >  1 file changed, 34 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > > index e6407e5..04a8877 100644
> > > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > > @@ -20,6 +20,8 @@
> > >  i2c2 = &i2c2;
> > >  i2c3 = &i2c3;
> > >  i2c4 = &i2c4;
> > > +spi0 = &qspi0;
> > > +spi1 = &qspi1;
> > >  };
> >
> > Geert can comment but I believe we are moving away from using aliases
> > in this way and that it would be best if the above hunk was dropped
> > from this patch.
> >
> > https://patchwork.kernel.org/patch/10644159/
>
> Geert, what do you want me to do here?

Please drop the aliases. Thanks!

Gr{oetje,eeting}s,

                        Geert
Fabrizio Castro Nov. 8, 2018, 10:31 a.m. UTC | #4
Hello Geert,

Thank you for your feedback!

> Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
>
> Hi Fabrizio,
>
> On Thu, Nov 8, 2018 at 11:22 AM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > > From: Simon Horman <horms@verge.net.au>
> > > Sent: 02 November 2018 11:50
> > > Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
> > >
> > > On Thu, Nov 01, 2018 at 12:35:04PM +0000, Fabrizio Castro wrote:
> > > > Add QSPI[01] support to the RZ/G1C SoC specific device tree.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > ---
> > > >  arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
> > > >  1 file changed, 34 insertions(+)
> > > >
> > > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > > > index e6407e5..04a8877 100644
> > > > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > > > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > > > @@ -20,6 +20,8 @@
> > > >  i2c2 = &i2c2;
> > > >  i2c3 = &i2c3;
> > > >  i2c4 = &i2c4;
> > > > +spi0 = &qspi0;
> > > > +spi1 = &qspi1;
> > > >  };
> > >
> > > Geert can comment but I believe we are moving away from using aliases
> > > in this way and that it would be best if the above hunk was dropped
> > > from this patch.
> > >
> > > https://patchwork.kernel.org/patch/10644159/
> >
> > Geert, what do you want me to do here?
>
> Please drop the aliases. Thanks!

Will do, will send a new version without the additional aliases.
My understanding is that your personal preference is to only leave debug console and ethernet,
shall I also  get rid of what was already upstreamed for RZ/G related boards that is not in line
with the new policy?

Thanks,
Fab

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Geert Uytterhoeven Nov. 8, 2018, 10:37 a.m. UTC | #5
Hi Fabrizio,

On Thu, Nov 8, 2018 at 11:31 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> > On Thu, Nov 8, 2018 at 11:22 AM Fabrizio Castro
> > <fabrizio.castro@bp.renesas.com> wrote:
> > > > From: Simon Horman <horms@verge.net.au>
> > > > Sent: 02 November 2018 11:50
> > > > Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
> > > >
> > > > On Thu, Nov 01, 2018 at 12:35:04PM +0000, Fabrizio Castro wrote:
> > > > > Add QSPI[01] support to the RZ/G1C SoC specific device tree.
> > > > >
> > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > > ---
> > > > >  arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
> > > > >  1 file changed, 34 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > > > > index e6407e5..04a8877 100644
> > > > > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > > > > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > > > > @@ -20,6 +20,8 @@
> > > > >  i2c2 = &i2c2;
> > > > >  i2c3 = &i2c3;
> > > > >  i2c4 = &i2c4;
> > > > > +spi0 = &qspi0;
> > > > > +spi1 = &qspi1;
> > > > >  };
> > > >
> > > > Geert can comment but I believe we are moving away from using aliases
> > > > in this way and that it would be best if the above hunk was dropped
> > > > from this patch.
> > > >
> > > > https://patchwork.kernel.org/patch/10644159/
> > >
> > > Geert, what do you want me to do here?
> >
> > Please drop the aliases. Thanks!
>
> Will do, will send a new version without the additional aliases.

Thanks!

> My understanding is that your personal preference is to only leave debug console and ethernet,

Labeled serial ports and primary Ethernet, so U-Boot knows which MAC address
property to update.

> shall I also  get rid of what was already upstreamed for RZ/G related boards that is not in line
> with the new policy?

I believe these are all serial ports, using aliases that match the documented
and/or labeled port names? So they don't have to be removed.

Gr{oetje,eeting}s,

                        Geert
Fabrizio Castro Nov. 8, 2018, 10:48 a.m. UTC | #6
Hi Geert,

Thank you for your feedback!

> Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
>
> Hi Fabrizio,
>
> On Thu, Nov 8, 2018 at 11:31 AM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > > On Thu, Nov 8, 2018 at 11:22 AM Fabrizio Castro
> > > <fabrizio.castro@bp.renesas.com> wrote:
> > > > > From: Simon Horman <horms@verge.net.au>
> > > > > Sent: 02 November 2018 11:50
> > > > > Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add QSPI support
> > > > >
> > > > > On Thu, Nov 01, 2018 at 12:35:04PM +0000, Fabrizio Castro wrote:
> > > > > > Add QSPI[01] support to the RZ/G1C SoC specific device tree.
> > > > > >
> > > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > > > ---
> > > > > >  arch/arm/boot/dts/r8a77470.dtsi | 34 ++++++++++++++++++++++++++++++++++
> > > > > >  1 file changed, 34 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> > > > > > index e6407e5..04a8877 100644
> > > > > > --- a/arch/arm/boot/dts/r8a77470.dtsi
> > > > > > +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > > > > > @@ -20,6 +20,8 @@
> > > > > >  i2c2 = &i2c2;
> > > > > >  i2c3 = &i2c3;
> > > > > >  i2c4 = &i2c4;
> > > > > > +spi0 = &qspi0;
> > > > > > +spi1 = &qspi1;
> > > > > >  };
> > > > >
> > > > > Geert can comment but I believe we are moving away from using aliases
> > > > > in this way and that it would be best if the above hunk was dropped
> > > > > from this patch.
> > > > >
> > > > > https://patchwork.kernel.org/patch/10644159/
> > > >
> > > > Geert, what do you want me to do here?
> > >
> > > Please drop the aliases. Thanks!
> >
> > Will do, will send a new version without the additional aliases.
>
> Thanks!
>
> > My understanding is that your personal preference is to only leave debug console and ethernet,
>
> Labeled serial ports and primary Ethernet, so U-Boot knows which MAC address
> property to update.
>
> > shall I also  get rid of what was already upstreamed for RZ/G related boards that is not in line
> > with the new policy?
>
> I believe these are all serial ports, using aliases that match the documented
> and/or labeled port names? So they don't have to be removed.

We have also been using aliases for i2c, spi (like in this case), vin, etc., for all of the RZ/G boards,
shall I get rid of those?

Cheers,
Fab

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index e6407e5..04a8877 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -20,6 +20,8 @@ 
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
+		spi0 = &qspi0;
+		spi1 = &qspi1;
 	};
 
 	cpus {
@@ -460,6 +462,38 @@ 
 			status = "disabled";
 		};
 
+		qspi0: spi@e6b10000 {
+			compatible = "renesas,qspi-r8a77470", "renesas,qspi";
+			reg = <0 0xe6b10000 0 0x2c>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 918>;
+			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+			       <&dmac1 0x17>, <&dmac1 0x18>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&cpg 918>;
+			status = "disabled";
+		};
+
+		qspi1: spi@ee200000 {
+			compatible = "renesas,qspi-r8a77470", "renesas,qspi";
+			reg = <0 0xee200000 0 0x2c>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 917>;
+			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+			       <&dmac1 0xd1>, <&dmac1 0xd2>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&cpg 917>;
+			status = "disabled";
+		};
+
 		scif0: serial@e6e60000 {
 			compatible = "renesas,scif-r8a77470",
 				     "renesas,rcar-gen2-scif", "renesas,scif";