From patchwork Wed Sep 20 18:28:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 816396 X-Patchwork-Delegate: cyrille.pitchen@atmel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LuvRP5lJ"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xy7bj0zz3z9sBd for ; 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Wed, 20 Sep 2017 18:30:43 +0000 Received: from mga09.intel.com ([134.134.136.24]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dujkt-000276-1b for linux-mtd@lists.infradead.org; Wed, 20 Sep 2017 18:30:00 +0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Sep 2017 11:29:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,422,1500966000"; d="scan'208";a="137603185" Received: from mgerlach-mobl.amr.corp.intel.com (HELO mgerlach-VirtualBox.amr.corp.intel.com) ([10.254.74.152]) by orsmga002.jf.intel.com with ESMTP; 20 Sep 2017 11:29:07 -0700 From: matthew.gerlach@linux.intel.com To: vndao@altera.com, dwmw2@infradead.org, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, marek.vasut@gmail.com, richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org, mark.rutland@arm.com, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, davem@davemloft.net, mchehab@kernel.org, linux-fpga@vger.kernel.org, tien.hock.loh@intel.com, hean.loong.ong@intel.com Subject: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg Date: Wed, 20 Sep 2017 11:28:59 -0700 Message-Id: <1505932139-2905-4-git-send-email-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com> References: <1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170920_112952_633196_4344F4ED X-CRM114-Status: GOOD ( 15.41 ) X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [134.134.136.24 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [134.134.136.24 listed in wl.mailspike.net] -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Gerlach MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Matthew Gerlach This patch is a work around for some non-standard behavior of EPCQ flash parts: https://www.altera.com/documentation/wtw1396921531042.html#wtw1396921651224 These flash parts are generally used to configure Intel/Altera FPGAs on power up. These parts report a JEDEC id of the Micron part at the core, but have a different number of dummy cycles than specified in the Micron data sheet. The number of required dummy cycles can be read from the Non-Volatile Configuration register. Signed-off-by: Matthew Gerlach --- drivers/mtd/spi-nor/altera-asmip2.c | 31 ++++++++++++++++++++++++++----- include/linux/mtd/altera-asmip2.h | 3 +++ 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/altera-asmip2.c b/drivers/mtd/spi-nor/altera-asmip2.c index a977765..d9cd807 100644 --- a/drivers/mtd/spi-nor/altera-asmip2.c +++ b/drivers/mtd/spi-nor/altera-asmip2.c @@ -40,6 +40,10 @@ #define QSPI_POLL_TIMEOUT_US 10000000 #define QSPI_POLL_INTERVAL_US 5 +#define SPINOR_OP_RD_NVCFG 0xb5 +#define NVCFG_DUMMY_SFT 12 +#define NVCFG_DUMMY_MASK 0xf + struct altera_asmip2 { void __iomem *csr_base; u32 num_flashes; @@ -231,7 +235,8 @@ static void altera_asmip2_unprep(struct spi_nor *nor, enum spi_nor_ops ops) } static int altera_asmip2_setup_banks(struct device *dev, - u32 bank, struct device_node *np) + u32 bank, struct device_node *np, + u32 flags) { const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_READ | @@ -241,6 +246,7 @@ static int altera_asmip2_setup_banks(struct device *dev, struct altera_asmip2 *q = dev_get_drvdata(dev); struct altera_asmip2_flash *flash; struct spi_nor *nor; + u16 nvcfg; int ret = 0; if (bank > q->num_flashes - 1) @@ -273,6 +279,20 @@ static int altera_asmip2_setup_banks(struct device *dev, return ret; } + if (flags & ALTERA_ASMIP2_FLASH_FLG_RD_NVCFG) { + ret = altera_asmip2_read_reg(nor, SPINOR_OP_RD_NVCFG, + (u8*)&nvcfg, sizeof(nvcfg)); + + if (ret) { + dev_err(nor->dev, + "failed to read NV Configuration register\n"); + return ret; + } + + nor->read_dummy = (nvcfg >> NVCFG_DUMMY_SFT) & NVCFG_DUMMY_MASK; + dev_info(nor->dev, "%s dummy %d\n", __func__, nor->read_dummy); + } + ret = mtd_device_register(&nor->mtd, NULL, 0); return ret; @@ -308,7 +328,7 @@ static int altera_asmip2_create(struct device *dev, void __iomem *csr_base) } static int altera_asmip2_add_bank(struct device *dev, - u32 bank, struct device_node *np) + u32 bank, struct device_node *np, u32 flags) { struct altera_asmip2 *q = dev_get_drvdata(dev); @@ -317,7 +337,7 @@ static int altera_asmip2_add_bank(struct device *dev, q->num_flashes++; - return altera_asmip2_setup_banks(dev, bank, np); + return altera_asmip2_setup_banks(dev, bank, np, flags); } static int altera_asmip2_remove_banks(struct device *dev) @@ -361,7 +381,8 @@ static int altera_asmip2_probe_with_pdata(struct platform_device *pdev, } for (i = 0; i < qdata->num_chip_sel; i++) { - ret = altera_asmip2_add_bank(dev, i, NULL); + ret = altera_asmip2_add_bank(dev, i, NULL, + qdata->flash_flags[i]); if (ret) { dev_err(dev, "failed to add qspi bank %d\n", ret); break; @@ -414,7 +435,7 @@ static int altera_asmip2_probe(struct platform_device *pdev) goto error; } - if (altera_asmip2_add_bank(dev, bank, pp)) { + if (altera_asmip2_add_bank(dev, bank, pp, 0)) { dev_err(dev, "failed to add bank %u\n", bank); goto error; } diff --git a/include/linux/mtd/altera-asmip2.h b/include/linux/mtd/altera-asmip2.h index 580c43c..185a9b2 100644 --- a/include/linux/mtd/altera-asmip2.h +++ b/include/linux/mtd/altera-asmip2.h @@ -16,9 +16,12 @@ #define ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP 3 #define ALTERA_ASMIP2_RESOURCE_SIZE 0x10 +#define ALTERA_ASMIP2_FLASH_FLG_RD_NVCFG BIT(0) + struct altera_asmip2_plat_data { void __iomem *csr_base; u32 num_chip_sel; + u32 flash_flags[ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP]; }; #endif