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Mon, 20 Feb 2017 19:30:45 -0800 (PST) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id s3sm37707713pgn.55.2017.02.20.19.30.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Feb 2017 19:30:45 -0800 (PST) From: Kamal Dasu To: linux-mtd@lists.infradead.org Subject: [PATCH V3, 2/2] mtd: nand: brcmnand: Check flash #WP pin status before nand erase/program Date: Mon, 20 Feb 2017 22:30:32 -0500 Message-Id: <1487647832-10544-2-git-send-email-kdasu.kdev@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487647832-10544-1-git-send-email-kdasu.kdev@gmail.com> References: <1487647832-10544-1-git-send-email-kdasu.kdev@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170220_193106_296991_082B5F63 X-CRM114-Status: GOOD ( 15.07 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c05:0:0:0:241 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (kdasu.kdev[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f.fainelli@gmail.com, Kamal Dasu , richard@nod.at, marek.vasut@gmail.com, bcm-kernel-feedback-list@broadcom.com, cyrille.pitchen@atmel.com, computersforpeace@gmail.com, dwmw2@infradead.org MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org brcmnand controller v6.x and v7.x lets driver to enable disable #WP pin via NAND_WP bit in CS_SELECT register. Driver implementation assumes that setting/resetting the bit would assert/de-assert #WP pin instantaneously from the flash part's perspective, and was proceeding to erase/program without verifying flash status byte for protection bit. In rigorous testing this was causing rare data corruptions with erase and/or subsequent programming. To fix this added verification logic to brcmandn_wp_set() by reading flash status and verifying protection bit indicating #WP pin status. The new logic makes sure controller as well as the flash is ready to accept commands. Signed-off-by: Kamal Dasu --- drivers/mtd/nand/brcmnand/brcmnand.c | 60 ++++++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c index c7c4efe..ad8733f 100644 --- a/drivers/mtd/nand/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/brcmnand/brcmnand.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -101,6 +102,8 @@ struct brcm_nand_dma_desc { #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) +#define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) + /* Controller feature flags */ enum { BRCMNAND_HAS_1K_SECTORS = BIT(0), @@ -765,12 +768,63 @@ enum { CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), }; -static int brcmnand_set_wp(struct brcmnand_host *host, int en) +static void bcmnand_ctrl_busy_poll(struct brcmnand_controller *ctrl, u32 mask, + u32 *reg_val) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(200); + u32 val; + + while (1) { + val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); + if ((val & mask) == mask) + break; + + if (time_after(jiffies, timeout)) { + dev_warn(ctrl->dev, "timeout on ctrl_ready %x\n", val); + break; + } + cpu_relax(); + } + + *reg_val = val; +} + +static inline void brcmnand_set_wp_reg(struct brcmnand_controller *ctrl, int en) { - struct brcmnand_controller *ctrl = host->ctrl; u32 val = en ? CS_SELECT_NAND_WP : 0; brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); +} + +static int brcmnand_set_wp(struct brcmnand_host *host, int en) +{ + struct brcmnand_controller *ctrl = host->ctrl; + struct mtd_info *mtd = nand_to_mtd(&host->chip); + struct nand_chip *chip = mtd_to_nand(mtd); + u32 val; + bool is_wp; + + /* + * make sure ctrl/flash ready before and after + * changing state of WP PIN + */ + bcmnand_ctrl_busy_poll(ctrl, NAND_CTRL_RDY | NAND_STATUS_READY, &val); + brcmnand_set_wp_reg(ctrl, en); + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + bcmnand_ctrl_busy_poll(ctrl, NAND_CTRL_RDY | NAND_STATUS_READY, &val); + /* NAND_STATUS_WP 0x80 = not protected, 0x00 = protected */ + is_wp = !(val & NAND_STATUS_WP); + + if (is_wp != en) { + u32 nand_wp = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); + + nand_wp &= CS_SELECT_NAND_WP; + dev_err_ratelimited(&host->pdev->dev, + "#WP %s sts:0x%x expected %s NAND_WP %d\n", + is_wp ? "On" : "Off", val & 0xff, + en ? "On" : "Off", nand_wp ? 1 : 0); + return -EINVAL; + } return 0; } @@ -1167,7 +1221,7 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) BUG_ON(ctrl->cmd_pending != 0); ctrl->cmd_pending = cmd; - intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); + bcmnand_ctrl_busy_poll(ctrl, NAND_CTRL_RDY, &intfc); WARN_ON(!(intfc & INTFC_CTLR_READY)); mb(); /* flush previous writes */