diff mbox

mtd: spi-nor: cqspi: Fix build on arches missing readsl/writesl

Message ID 1470143447-11351-1-git-send-email-marex@denx.de
State Accepted
Commit 0cf1725676a97fc8b4dd88794ea0acc1325b4fb7
Headers show

Commit Message

Marek Vasut Aug. 2, 2016, 1:10 p.m. UTC
The x86-64 and some other architectures are missing readsl/writesl
functions, so this driver won't build on them. Use a more portable
ioread32_rep()/iowrite32_rep() instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alan Tull <atull@opensource.altera.com>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Graham Moore <grmoore@opensource.altera.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
Suggested-by: Stefan Roese <sr@denx.de>
---
 drivers/mtd/spi-nor/Kconfig           | 2 +-
 drivers/mtd/spi-nor/cadence-quadspi.c | 6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

Comments

Marek Vasut Oct. 17, 2016, 4:39 p.m. UTC | #1
On 08/02/2016 03:10 PM, Marek Vasut wrote:
> The x86-64 and some other architectures are missing readsl/writesl
> functions, so this driver won't build on them. Use a more portable
> ioread32_rep()/iowrite32_rep() instead.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Alan Tull <atull@opensource.altera.com>
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Graham Moore <grmoore@opensource.altera.com>
> Cc: Vignesh R <vigneshr@ti.com>
> Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
> Suggested-by: Stefan Roese <sr@denx.de>
> ---

Bump ?

>  drivers/mtd/spi-nor/Kconfig           | 2 +-
>  drivers/mtd/spi-nor/cadence-quadspi.c | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 4a682ee..1e6f037 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -40,7 +40,7 @@ config SPI_ATMEL_QUADSPI
>  
>  config SPI_CADENCE_QUADSPI
>  	tristate "Cadence Quad SPI controller"
> -	depends on OF && ARM
> +	depends on OF && (ARM || COMPILE_TEST)
>  	help
>  	  Enable support for the Cadence Quad SPI Flash controller.
>  
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index d403ba7..08c9483 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -526,7 +526,8 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
>  			bytes_to_read *= cqspi->fifo_width;
>  			bytes_to_read = bytes_to_read > remaining ?
>  					remaining : bytes_to_read;
> -			readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
> +			ioread32_rep(ahb_base, rxbuf,
> +				     DIV_ROUND_UP(bytes_to_read, 4));
>  			rxbuf += bytes_to_read;
>  			remaining -= bytes_to_read;
>  			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
> @@ -610,7 +611,8 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> -		writesl(cqspi->ahb_base, txbuf, DIV_ROUND_UP(write_bytes, 4));
> +		iowrite32_rep(cqspi->ahb_base, txbuf,
> +			      DIV_ROUND_UP(write_bytes, 4));
>  
>  		ret = wait_for_completion_timeout(&cqspi->transfer_complete,
>  						  msecs_to_jiffies
>
Marek Vasut Nov. 25, 2016, 7:10 p.m. UTC | #2
On 08/02/2016 03:10 PM, Marek Vasut wrote:
> The x86-64 and some other architectures are missing readsl/writesl
> functions, so this driver won't build on them. Use a more portable
> ioread32_rep()/iowrite32_rep() instead.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Alan Tull <atull@opensource.altera.com>
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Graham Moore <grmoore@opensource.altera.com>
> Cc: Vignesh R <vigneshr@ti.com>
> Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
> Suggested-by: Stefan Roese <sr@denx.de>

Maybe you can review and pick this one finally ?

> ---
>  drivers/mtd/spi-nor/Kconfig           | 2 +-
>  drivers/mtd/spi-nor/cadence-quadspi.c | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 4a682ee..1e6f037 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -40,7 +40,7 @@ config SPI_ATMEL_QUADSPI
>  
>  config SPI_CADENCE_QUADSPI
>  	tristate "Cadence Quad SPI controller"
> -	depends on OF && ARM
> +	depends on OF && (ARM || COMPILE_TEST)
>  	help
>  	  Enable support for the Cadence Quad SPI Flash controller.
>  
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index d403ba7..08c9483 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -526,7 +526,8 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
>  			bytes_to_read *= cqspi->fifo_width;
>  			bytes_to_read = bytes_to_read > remaining ?
>  					remaining : bytes_to_read;
> -			readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
> +			ioread32_rep(ahb_base, rxbuf,
> +				     DIV_ROUND_UP(bytes_to_read, 4));
>  			rxbuf += bytes_to_read;
>  			remaining -= bytes_to_read;
>  			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
> @@ -610,7 +611,8 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> -		writesl(cqspi->ahb_base, txbuf, DIV_ROUND_UP(write_bytes, 4));
> +		iowrite32_rep(cqspi->ahb_base, txbuf,
> +			      DIV_ROUND_UP(write_bytes, 4));
>  
>  		ret = wait_for_completion_timeout(&cqspi->transfer_complete,
>  						  msecs_to_jiffies
>
Cyrille Pitchen Nov. 30, 2016, 2:36 p.m. UTC | #3
Le 02/08/2016 à 15:10, Marek Vasut a écrit :
> The x86-64 and some other architectures are missing readsl/writesl
> functions, so this driver won't build on them. Use a more portable
> ioread32_rep()/iowrite32_rep() instead.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Alan Tull <atull@opensource.altera.com>
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Graham Moore <grmoore@opensource.altera.com>
> Cc: Vignesh R <vigneshr@ti.com>
> Cc: Yves Vandervennet <yvanderv@opensource.altera.com>
> Suggested-by: Stefan Roese <sr@denx.de>
Applied to git://github.com/spi-nor/linux.git

Thanks!

> ---
>  drivers/mtd/spi-nor/Kconfig           | 2 +-
>  drivers/mtd/spi-nor/cadence-quadspi.c | 6 ++++--
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> index 4a682ee..1e6f037 100644
> --- a/drivers/mtd/spi-nor/Kconfig
> +++ b/drivers/mtd/spi-nor/Kconfig
> @@ -40,7 +40,7 @@ config SPI_ATMEL_QUADSPI
>  
>  config SPI_CADENCE_QUADSPI
>  	tristate "Cadence Quad SPI controller"
> -	depends on OF && ARM
> +	depends on OF && (ARM || COMPILE_TEST)
>  	help
>  	  Enable support for the Cadence Quad SPI Flash controller.
>  
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index d403ba7..08c9483 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -526,7 +526,8 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
>  			bytes_to_read *= cqspi->fifo_width;
>  			bytes_to_read = bytes_to_read > remaining ?
>  					remaining : bytes_to_read;
> -			readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
> +			ioread32_rep(ahb_base, rxbuf,
> +				     DIV_ROUND_UP(bytes_to_read, 4));
>  			rxbuf += bytes_to_read;
>  			remaining -= bytes_to_read;
>  			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
> @@ -610,7 +611,8 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
>  
>  	while (remaining > 0) {
>  		write_bytes = remaining > page_size ? page_size : remaining;
> -		writesl(cqspi->ahb_base, txbuf, DIV_ROUND_UP(write_bytes, 4));
> +		iowrite32_rep(cqspi->ahb_base, txbuf,
> +			      DIV_ROUND_UP(write_bytes, 4));
>  
>  		ret = wait_for_completion_timeout(&cqspi->transfer_complete,
>  						  msecs_to_jiffies
>
diff mbox

Patch

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 4a682ee..1e6f037 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -40,7 +40,7 @@  config SPI_ATMEL_QUADSPI
 
 config SPI_CADENCE_QUADSPI
 	tristate "Cadence Quad SPI controller"
-	depends on OF && ARM
+	depends on OF && (ARM || COMPILE_TEST)
 	help
 	  Enable support for the Cadence Quad SPI Flash controller.
 
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index d403ba7..08c9483 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -526,7 +526,8 @@  static int cqspi_indirect_read_execute(struct spi_nor *nor,
 			bytes_to_read *= cqspi->fifo_width;
 			bytes_to_read = bytes_to_read > remaining ?
 					remaining : bytes_to_read;
-			readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
+			ioread32_rep(ahb_base, rxbuf,
+				     DIV_ROUND_UP(bytes_to_read, 4));
 			rxbuf += bytes_to_read;
 			remaining -= bytes_to_read;
 			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
@@ -610,7 +611,8 @@  static int cqspi_indirect_write_execute(struct spi_nor *nor,
 
 	while (remaining > 0) {
 		write_bytes = remaining > page_size ? page_size : remaining;
-		writesl(cqspi->ahb_base, txbuf, DIV_ROUND_UP(write_bytes, 4));
+		iowrite32_rep(cqspi->ahb_base, txbuf,
+			      DIV_ROUND_UP(write_bytes, 4));
 
 		ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 						  msecs_to_jiffies